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v3.0.6 3.0.6 - 2021-01-20 ================== Fixed ----- - sw: open_by_lun() conversion from LUN to ID
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v3.0.7 3.0.7 - 2021-02-24 ================== Added ----- - sw: show the input status from the fmc-fdelay-status tool - sw: use the fmc-fdelay-input tool to change the input status Fixed ----- - sw: make clear in the tools' help message that the device ID is an hexadecimal number
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v3.0.8 3.0.8 - 2021-03-17 ================== Changed ------- - hdl: svec-base updated to 2.0, for the FD there are no incompatible changes - sw,hdl: compact memory map [we know, do not ask]
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v3.0.9 3.0.9 - 2022-12-14 ================== Added ----- - hdl: bitstreams now published under https://be-cem-edl.web.cern.ch/ - doc: now published under https://be-cem-edl.web.cern.ch/ - sw: support for newer Linux kernels Changed ------- - bld: many improvements to CI - bld: build system cleanup - hdl: update to latest releases of all dependencies - hdl: top-level VHDL module names are now more consistent and descriptive Fixed ----- - hdl: WR ready bit in TCR register now always shows the validity of WR time - sw: output pulse duty cycle now properly set to 50% by default
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v3.1.0 3.1.0 - 2023-11-24 ================== Added ----- - sw: support for HWMON API to expose Temperature readings (#20) Changed ------- - ci: many improvements to pytest tests - bld: use common EDL CI pipelines for software and gateware (#24, #25) - hdl: automatic convention version assignment (#19) - hdl: small register balancing to help with timing (#28) - sw: driver now reports error when FPGA is not configured (#23) - sw: tools now statically link to library (#27)
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v3.1.1 3.1.1 - 2024-02-05 ================== Fixed ----- - sw: header files directory was erroneously set to a different value that it was in the past.
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