Project description
The FMC DEL 1ns 4cha delay module will take in a TTL trigger signal and will send it out to four different outputs. The delay from the trigger input to each of the outputs can be set independently in a range from 500 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter IC from the European company Acam.
side_a_s.JPG
Top view of the FMC Delay card with SMC connectors. Final design will
use LEMO 00 connectors*
Bottom view
Specifications
- Full details in the Functional system specifications
Specification overview
Parameter | Value |
Channels | 1 trigger input, 4 outputs |
Connectors | LEMO 00 for all signals |
Signal level | TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate |
Operating modes |
Pulse delay: on trigger, generates a pulse or series of pulses of given width and repetition rate on chosen outputs after a certain time programmed by the user. Single channel TDC: time tags incoming trigger pulses available via a circular buffer. Pulse generator: produces a pulse or a series of pulses of arbitrary length and repetition rate starting at a given UTC/TAI time. |
Minimum input pulse width | 100 ns. Pulses below 24 ns are ignored. |
Maximum input pulse rate | 2 MHz (minimum pulse spacing: 50 ns) |
Output pulse width | 50 ns - 1 s (10 ps resolution) |
Output pulse spacing | 100 ns - 1 s (10 ps resolution) |
Output pulse repeat count (train generation) | 1 - 65536 pulses or infinity (continuous mode) |
Timebase accuracy | ± 4ppm The timebase from a local TCXO on FMC card needs calibration. The 4ppm accuracy is the one of the on-board TCXO. Cesium-quality accuracy will be reached when used on a White Rabbit enabled FMC carrier. |
TDC Resolution | 28 ps |
TDC Precision (std. dev) | 55 ps |
Accuracy | ± (300 ps + timebase accuracy) |
Time tag buffer | 1024-entries circular buffer with time tags for input/output pulses. Buffer interrupt (with timeout/threshold coalescing) |
Detailed project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-02267
- Card aka FMC6 and Fine Delay
- LHC Equipment name: CFFIB
- Controls Configuration Database entry
- Controls EDMS page
Contacts
Commercial producer
- INCAA Computers, Netherlands
- FMC Delay, Creotech, Poland
General question about project
- Erik van der Bij - CERN
Project Status
Date | Event |
22-04-2010 | Start working on project. |
30-04-2010 | First meeting with N. Voumard to fine-tune functional specs. |
20-05-2010 | Second functional specs meeting with the ABT team. |
11-06-2010 | Order 4384595 made for design of the module. |
15-06-2010 | Final functional specification review meeting held. Resulted in minor modifications. |
30-06-2010 | Technical specification draft finished. |
17-08-2010 | First schematics review held. ReviewFineDelayFMC17082010 |
03-09-2010 | Schematics revised. Waiting for a new design review. |
10-11-2010 | Second schematics review held. ReviewFineDelayFMC10112010 |
12-11-2010 | Comments on review received. Re-commented on it. FMC10112010_improvements v5 |
25-11-2010 | Updated schematics and comments received. ReviewFineDelayFMC10112010-improvements |
25-11-2010 | Comments on updated schematics. ReviewFineDelayFMC25112010 |
30-11-2010 | Updated schematics and comments received. ReviewFineDelayFMC25112010-improvements |
13-12-2010 | First version of PCB layout expected by 17 December. |
14-01-2011 | Spec change for minimum delay: 500 ns. PCB layout almost finished, waiting for some symbols. |
18-01-2011 | PCB layout received. Review on 19-01-2011. |
18-01-2011 | Changelog for the PCB/schematics published: Changelog-19012010 |
20-01-2011 | PCB review held. V1 layout ready (SVN revision: 18) Changelog-20012011 |
28-01-2011 | Empty PCB should arrive on 1 February. Requested design office to review files. |
03-02-2011 | Prototype PCB assembled and ready for HDL development. ID EEPROM works. |
14-02-2011 | Design being reviewed by CERN's design office. |
21-02-2011 | HDL development on-going. |
02-03-2011 | Returned corrections in schematics to design office. |
18-03-2011 | Design checked and available in EDMS. |
19-04-2011 | Rather high jitter in prototype. Will improve layout of supply to ACCAM chip. |
05-05-2011 | V2 schematics and layout available for review: Changelog-05052011 |
06-05-2011 | V2 review held. Reduce number of R values, no large ceramic C, 20 MHz osc instead of 25 MHz. |
08-06-2011 | Files sent to CERN's design office for review and front-panel design. |
14-07-2011 | V2 design ready. Will produce 4 prototypes, after correcting OHL licence and removal of CERN logo. |
16-08-2011 | PCB ready by 19-08-2011. Assembly can start. |
31-08-2011 | Received assembled prototype of V2. |
02-09-2011 | V2 works. |
16-11-2011 | V2 demoed on SPEC. Considering changing output driver to have less cross-talk. |
09-01-2012 | V3 proto with changed output driver being tested. Preparing price enquiry. |
26-01-2012 | Price enquiry sent out. Deadline 24 February. 40 cards expected by 24 August. |
03-02-2012 | In parallel assemble 10 boards for urgent project. |
24-02-2012 | One card sent for writing Linux driver. Firmware available, but needs finalisation. |
01-03-2012 | Third schematics and PCB review held. ReviewFineDelayFMC02032012 |
07-03-2012 | Order placed with INCAA for 40 cards. Delivery: preseries (10) end June; series (30) end August. |
Erik van der Bij - 7 March 2012