The mail below includes most of the review comments of the review held
on 17 August 2010
From: Matthieu Cattin
Sent: Wednesday 18 August 2010 10:50
To: Grzegorz Kasprowicz
Cc: Erik Van Der Bij; Pablo Alvarez Sanchez; Tomasz Wlostowski; Maciej
Subject: Re: RE : FW: Fine Delay FMC
On Tue, 17 Aug 2010, Grzegorz Kasprowicz wrote:
> On 17 August 2010 23:22, Matthieu Cattin <Matthieu.Cattin@cern.ch>
>> Hi Greg,
>> Here are my comments:
>> FMC delay top:
>> - LED2 (PLL_STATUS from U_clock_generator) is not connected.
> sure, it should be renamed to LED1, fixed
I'd rather use this LED to indicate an input trigger than the PLL
What do you think?
>> - LA06_P, LA01_N_CC and LA01_P_CC (I2C bus for thermometer and
>> are not connected to the FMC connector.
> anyway, this generator will be removed due to its cost.
> Since we have PLL there is no need to have adjustable clock.
> simple 25MHz , preferably TCXO oscillator would do the job.
> Thermometer will be connected directly to the I2C bus of the FMC card
> is addressable.
>> - PD (AD9516 pin 24) is active low and is connected to GND, the
>> always powered down. => PD has an internal pull-up.
> OK,so there is a bug in a library - it is not marked as active low.
The symbol is OK, but there is an option in Altium called "Single '\'
Negation" that should be activated in DXP > Preferences > Schematic >
>> - SYNC (AD9516 pin 8) is active low too. => SYCN has an internal
> OK, the resistor can be not soldered then or removed
As SYNC is not used, I think you can remove the resistor.
>> - Is REF_SEL useful as the reference input is differential?
> Ok, my fault.
> Since TCXO has single ended output, now REF2 can be used as ext
> FMC does not provide any SE clock source. Shall we use this option at
> I connected it mainly because I had double switch :)
You can always connect REF2 to an FMC data line.
But I don't see any use for it.
>> - BTW, why using a Si570 as reference for the AD9516?
> I don't remember, there was a discussion about it. At that moment I
> plan a PLL at all. It will be replaced by low cost crystal since we
>> - I don't understand the VDDC_TDC regulator connection.
>> Shouldn't VDDC_TDC be connected to 3.3V?
> It is correct - I copied this from working device - BPIM board that I
> for CMS.
> We discovered that it locks faster when both voltages are regulated
> internal PLL.
Ok, good to know.
>> Output buffer:
>> - The OE (output enable) logic looks strange to me.
>> Shouldn't you use an OR gate and connect OEn to RESET instead of
>> This would disable the outputs during reset and on request
> well, it depends if you want to have output disable signal active low
> At the moment both of them are active low.
> But you are right - using OR gate is safer.
> But even better is using NAND - both inputs must be high to enable.
> component exist in CERN library.
> So during reset phase outputs will be disabled.
> I added pull-down resistor to it.
We can use a NAND gate then. But you'll have to rename OUTPUT_DISABLE
>> - The functional specification says "1 input, selectable between
>> and FMC connector" but I don't see the input from the FMC. Or do I
> Oh, it's me who missed it.