Review handling and comments
General
- Print out the power and ground list for all ICs and check if they’re
correctly connected
○ Will be done for the next draw - Print out the netlist, sort alphabetically and check for any
inconsistencies (in naming, bus signals all used).
○ Will be done for the next draw - Blocks and symbols should be aligned to make look cleaner
○ Done - Are the symbols all from the CERN design office library?
○ Yes, they are - All names should be shared accross sheets
○ Yes they are. But maybe a slight change should be considered to avoid Altium's warnings "has multiple names" - Positive and Negative voltage levels should be written with P and N
in front of instead of +-
○ Done
BOM
- Still many components that are used once
○ Taken into account. But hints/advices are welcomed to tackle this issue. - 30K, 270K 430K only used once
○ See above - 10 uF in polarised and unpolarised
○ Changed, same capacitor used uniformly - 4k01 0.1% tolerance? Is expensive
○ Indeed, it has been changed - 100 Ohm in different packages?
○ Changed - DIL network of 10K, likely easier to route and cheaper to use
discrete SMD resistors. DIL = manual soldering
○ Network resistors have been suggested to spare space - 10uH can possibly be made with 2 x 4.7uH in series
○ Changed, with the LT1931A - LED, use same, double LED as used on other FMC mezzanines. Lowers
risk for mechanics, we/others may have stock if needed
○ Using the same LED as the one present in the FMC ADC
Top View
- COMP_OUT_02_P/N are not connected on FMC_Connector (but are used
on IN_0/IN1 input stage block!)
○ Done
- OUT_8&9 is a ‘dangerous’ name with the &-sign. Risk that tools
handle it badly.
○ Done
- OUT8 and OUT9 should not be called like that. More like
Dry_contact
○ Changed for BIP_OUT. But Dry_contact would suit perfectly. - Move OUT_0-7 down from output stage block
○ Changed - Is it really the best to link all SDI/SDO of all blocks? Speed is no
problem? Risk of anything going wrong?
○ It has been calculated, DAC requires 24 bits to update all channels and the next bits are sent to the SDO.
is 24bits/channel*20channels.
The problem is the low amount of user defined pins which oblige this kind of design. - DAC_OUT_X are not present on Input_Stage blocks
○ Changed - OWN should be changed by FP
○ Changed - Wires for right hand part of blocks
○ Changed - Arrange to make it cleaner
○ Changed
h2. Input Stage
- COMP_OUT1_N and COMP_OUT1_P are reversed. Same for OUT3 N/P
- Check for LVDS levels respect
- Use all four symbols in the same way to prevent this type of problems
- RSPECL outputs which are emitter follower. It needs termination (pull-down) to VTT. Can FPGA support such termination?
- Check that there are enough capacitors
- Diodes are not correctly placed (pin 3 is connected to both N5V0 and P5V0)
- There should be only one input input format, copied 4 times. Now, it is misleading with inverted comparator
- Do LVDS lines require pull-up?
- VADJ must be first to prevent negative voltage at the FPGA inputs
- Mark on page that Vadj is 2V5
- Mark on page how hysteresis circuit works, how much (dependent on DAC value?)
- IC23A and IC23B, but power block is IC7C
- 4k02 value chosen for what reason? 0.1%
- align components
- add hysteresis notes
- More decoupling capacitors close to IC6, IC4, IC22 and IC24.
Output stage
- Cannot drive the 244 directly from the FMC connector? Saves components and gains speed.
- No power of the hex schmitt trigger. Compatible with VADJ?
- change names to make it more readable
- align power at bottom, align OUTs on the left
- 10k resistor probably not needed
- LA_XX names not in front of their IC number
- check of the compatibility with 1.8 and 2.5V
DAC
- cleanup, make better readable. Gnd symbols are missing
- Precision reference voltage required? (P5V0)
- Capacitor for P5V0
- Notes should be written
FMC Connector
- COMP_OUT02 missing
- X at LA_02P/N
- Add note that works with Vadj=2V5 and 1V8
- Foresee decoupling capacitors near the FMC connector (allowing power pins to work as signal return too).
- Make names fit in blocks of connectors
- Align connections
I2C
- IC25 SCL and SDA are both connected to I2C_SCL
- GA1 should connect to A0, GA0 should connect to A1 (Observation 5.22 FMC spec)
- Add unique ID/thermometer chip as used on all other OH FMC cards
- Use SMD separate resistors
- No decoupling for IC2
- Twice R4 near LED
- make TERM_EN11/12 look same as others.
- Move all pull-ups, up for easier understanding of schematics
- All names should be the same
- Another LED exists
- P5V0 requires capacitor
- Pull-up for I2C
Supply stage
- 5V_P is used for the protection. But with the 10K in series it will not protect anything. Same for N5V_P
- Step_up from 3.3V to 5V to have enough amperes
- C_23 should be inverted
- Add note how 5V_P is used
- Follow OHWR power net names: P5V0, N5V0, etc (less errors than ‘-‘, more standard)
- Srange reference with D5 and D6, it will not be stable (N3.5mV/K)
- Missing input cap of IC19, it may oscillate
- Generation of 7V from 12V. IVcci of LMH comp is 8mA, 20 of them yield 160mA. If we multiply (12-7) it gives 0.8W of wasted power.
- The same applies to P5V0, if we set all 8 outputs high driving 50Ohm to GND, it yields 8****(12-5)=0.8A*7V=5.6W. Use of 7V converter then LDO to produce 5V.
- Why 2x4.7uF for N12V0, and only one for N5V0?
- Strange crossing at Vin of IC18/IC19, pin 5
- Make sure EP of IC21 should connect to 7V
- 10pF is the only one, may possibly use another value?
- cosmetics: L1/L3 should be in middle of line, C30 over other text
- add note for calculation
- align things
Most of the written comments are derivated from an email of Erik Van Der
Bij and Gzegorz Kasprowicz.
Special thanks to: Erik Van Der Bij, Grzegorz Daniluk, Evangelia
Gousiou, Denia Bouhired-Ferrag, Grzegorz Kasprowicz