FMC DIO 10I8O
Project description
The FMC DIO 10i8o is an I/O card in FMC form-factor. This card uses a
low-pint count (LPC) connector.
It's 10 inputs use fast differential comparators (propagation delay < 1
ns) with 12-bit DAC to set references. The 8 outputs are LVTTL level.
There exist two interfaces for the FCS8 connector, one Patch-panel and one Breakout-board.
Other FMC projects and the FMC standard are described in FMC Projects .
Main features
* FMC low-pin count (LPC)
- Supported Vadj 1.8V and 2.5V
- FMC connectivity: all 34 differential pairs connected, I2C
* Inputs - 10 x high speed input channels with 2 comparators per channel (to measure risetime or positive and negative thresholds)
- input levels: +-5V nominal (tolerated 15V during 5us)
- Programmable threshold: +-5V using DAC with 12bit precision (DAC7716SFPB)
- Input bandwidth: 350MHz
- Selectable: High-impedance (10kOhm) or 50 Ohm
* Outputs: - 8 x digital LVTTL
** 2 x Quad LVDS receiver (MAX9122EUE) + 1 x Octal line driver (74LVC2244ABQ) - 2 x isolated contact for PLC fail-safe functionality
- Independent I2C for external communication (Patch panel,...)
* Connectivity - Front SAMTEC FCS8-20-01-L-S-A-TR connector
- Optional 2-pin Lemo 00 connector (LEMO EPG.00.302.NLN) for external
I2C bus -> can be used as general purpose I2C master
* Comparators - 5 x LMH7324SQ/NOPB Quad high speed comparator
- Number of comparators: 20 (2 per input channel)
- Voltage references: 20 (1 per comparator)
- Communication with FPGA: LVDS, 1 pair per channel
* ID, memory - Unique 64-bit identifier, 1.8V and one-wire compatible (DS2411R+)
- 64 kbit EEPROM connected for storing application parameters
(24AA64T-I/MC)
* 8-layer PCB
Project information
- Patch panel is described in this page: Patch-panel and available on EDA-03388-V1
- Breakout board is described in this page: Breakout-board and available on EDA-03341-V1
- Documentation of the latest FMC DIO10I8O V3 is available on EDA-03287-V3
- Several components were changed on EDA-03287-V2 to make it functional, so there's now an unofficial EDA-03287-V2.1
- Documentation of the FMC DIO10I8O V2 is available on EDA-03287-V2
- Documentation of the FMC DIO10I8O V1 is available on EDA-03287-V1
- Schematics, second draft
- Schematics, first draft
- Hysteresis calculation and simulation
Contacts
- Pieter Van Trappen
Project
Commercial producers
- none yet
Project Status
Date | Event |
---|---|
02-06-2015 | First ideas for the I/O card. |
27-07-2015 | Creation of Open Hardware project, selection of connector and fast comparator. |
04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice |
08-09-2015 | First schematics and reviewing process |
02-11-2015 | Schematics, first draft available |
06-11-2015 | Review with BE-CO team and its corrections |
24-11-2015 | Schematics, second draft available |
26-11-2015 | Review of the PCB-layout from BE/CO department |
02-12-2015 | Schematics sent to CERN design office for PCB layout |
28-01-2016 | FMC V1 in production |
25-02-2016 | Breakout board created |
21-03-2016 | VDHL code writing process started |
27-04-2016 | Reception of two FMC V1 prototypes, beginning of hardware and software tests |
25-07-2016 | Patch panel sent to production |
01-09-2016 | FMC V2 required because problems with LMH7324 availability and incorrect power supply components |
16-09-2016 | FMC V2 with new schematics and new layout |
20-10-2016 | Production of 6x FMC V2 samples |
20-01-2017 | designer Simon has left CERN, Pieter taking over |
10-08-2017 | Production launch of pre-series: 12x FMC V3 |
10-10-2017 | Pre-series arrived, tests ongoing - so far so good |
21 October 2016