FMC DIO 10i 8o I/O module
FmcDIO10i8o is an I/O card in FMC form-factor. It's 10 inputs use fast differential comparators (propagation delay < 1 ns) with 12-bit DAC to set references. The 8 outputs are TTL level.
Functional specifications
Parameter | Value |
Inputs | 10 high speed inputs and comparators |
Outputs | 8 TTL |
Number of comparators | 20 (2 per input channel) |
Comparator reference | 20 (1 per comparator) |
Comparator input bandwidth | 350MHz |
Comparator input levels | ±5V |
Comparators to FPGA | LVDS, 1 pair per channel |
FMC to carrier interface | Low pin count (LPC) |
Supported Vadj | 1.8V and 2.5V |
Input impedance | High-impedance or 50 Ohm (selectable) |
Programmable threshold | From 5V to -5V using DAC with 5mV precision |
Digital Outputs | TTL line driver |
DAC resolution | 12bits |
Sampling rate | 166kHz |
Insulation | Output isolated contact |
Project information
- First draw schematics might be found here: https://www.ohwr.org/project/fmc-dio-10i-8o/wikis/Documents/Schematics-first-draft. Its reviewing with a BE-CO team is available here: Review-first-draw .
- Hysteresis calculation and simulation might be found here Hysteresis
- Software
- Frequently Asked Questions
- Users
Contacts
Commercial producers
- none yet
Project
- Simon Andre J Uyttenhove <simon.uyttenhove@cern.ch>
- Pieter Van Trappen <pieter.van.trappen@cern.ch>
Project Status
Date | Event |
02-06-2015 | First ideas for the I/O card. |
27-07-2015 | Creation of Open Hardware project, selection of connector and fast comparator. |
04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice |
08-09-2015 | First schematics and reviewing process |
22-09-2015 | Second draw of the schematics and reviewing process |
06-11-2015 | Review with BE-CO, available here Review-first-draw |
16-11-2015 | Schematics sent to CERN design office for PCB layout and production of two samples |
01-01-2016 | Reception of PCB samples and tests |
06 November 2015