FMC DIO 10i8o
Project description
The FMC DIO 10i8o is an I/O card in FMC form-factor. This card uses a
low-pint count (LPC) connector.
It's 10 inputs use fast differential comparators (propagation delay < 1
ns) with 12-bit DAC to set references. The 8 outputs are LVTTL level.
Other FMC projects and the FMC standard are described in FMC Projects .
Main features
* FMC low-pin count (LPC)
- Supported Vadj 1.8V and 2.5V
- FMC connectivity: all 34 differential pairs connected, I2C
* Inputs - 10 x high speed inputs and comparators
- Programmable threshold: 10V to -10V using DAC with 12bit precision
- Input bandwidth: 350MHz
- Selectable: High-impedance or 50 Ohm
* Outputs: - 8 x digital LVTTL
** 2 x Quad LVDS receiver (MAX9122EUE) + 1 x Octal line driver (74LVC2244ABQ) - 2 x isolated contact for PLC fail-safe functionality
* Comparators - 10 x LMH7322SQ/NOPB Quad high speed comparator
- Number of comparators: 20 (2 per input channel)
- Voltage references: 20 (1 per comparator)
- Communication with FPGA: LVDS, 1 pair per channel
* ID, memory and input impedance - Unique 64-bit identifier, 1.8V and one-wire compatible (DS2411R+)
- 64 kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
- Input impedance with high impedance and 50Ohm selectable
* 8-layer PCB
Project information
- Documentation of the FMC second version is available on EDA-03287-V2
- Documentation of the first prototype is available OHWR or on EDA-03287-V1-1
- Second draw schematics
- First draw schematics
- Hysteresis calculation and simulation
- Software
- Frequently Asked Questions
- Users
Contacts
Commercial producers
- none yet
Project
- Simon Andre J Uyttenhove <simon.uyttenhove@cern.ch>
- Pieter Van Trappen <pieter.van.trappen@cern.ch>
Project Status
| Date| * Event *|
| 02-06-2015 | First ideas for the I/O card. |
| 27-07-2015 | Creation of Open Hardware project, selection of connector
and fast comparator. |
| 04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice
|
| 08-09-2015 | First schematics and reviewing process |
| 22-09-2015 | First schematics improved |
| 06-11-2015 | Review with BE-CO, available here
Review-first-draw
(Corrections-after-Review-first-draw)
| 24-11-2015 | Second draw of the
schematics available |
| 16-11-2015 | Schematics sent to CERN design office for PCB layout and
production of two samples |
| 26-11-2015 | Review of the PCB-layout from BE/CO department |
| 27-11-2015 | PCB prototypes in
production |
| 27-01-2016 | FMC breakout board created |
| 21-03-2016 | VDHL code writing process started |
| 27-04-2016 | Reception of PCB samples, beginning of hardware and
software tests |
| 01-09-2016 | V2 required because problems with LMH7324 disponibility
and incorrect power supplies |
| 16-09-2016 | V2 with new schematics and new layout |
| 17-10-2016 | Production of FMC V2 samples |
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12 October 2016