FMC DIO 10i 8o I/O module
FmcDIO10i8o is an I/O card in FMC form-factor. It's 10 inputs use fast differential comparators (propagation delay < 1 ns) with 12-bit DAC to set references. The 8 outputs are TTL level.
Main features
* Inputs: 10 high speed inputs and comparators
* Outputs: 8 LVTTL
* Number of comparators: 20 (2 per input channel)
* Comparator reference | 20 (1 per comparator)
* Comparators to FPGA | LVDS, 1 pair per channel
* Comparator input bandwidth | 350MHz
* Comparator input levels | ±5V
* FMC to carrier interface | Low pin count (LPC)
* Supported Vadj| 1.8V and 2.5V
* Input impedance | High-impedance or 50 Ohm (selectable)
* Programmable threshold | From 5V to -5V using DAC with 5mV
precision
* Digital Outputs | TTL line driver
* DAC resolution | 12bits
* Sampling rate | 166kHz
* Insulation | Output isolated contact
Project information
- First Prototype
- Second draw schematics
- First draw schematics
- Hysteresis calculation and simulation
- Software
- Frequently Asked Questions
- Users
Contacts
Commercial producers
- none yet
Project
- Simon Andre J Uyttenhove <simon.uyttenhove@cern.ch>
- Pieter Van Trappen <pieter.van.trappen@cern.ch>
Project Status
Date | Event |
02-06-2015 | First ideas for the I/O card. |
27-07-2015 | Creation of Open Hardware project, selection of connector and fast comparator. |
04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice |
08-09-2015 | First schematics and reviewing process |
22-09-2015 | First schematics improved |
06-11-2015 | Review with BE-CO, available here Review-first-draw (Corrections-after-Review-first-draw) |
24-11-2015 | Second draw of the schematics available |
16-11-2015 | Schematics sent to CERN design office for PCB layout and production of two samples |
26-11-2015 | Review of the PCB-layout from BE/CO department |
27-11-2015 | PCB prototypes in production |
21-03-2016 | VDHL code started |
06-04-2016 | Reception of PCB samples and tests |
26 January 2016