FMC DIO 10i8o
Project description
The FMC DIO 10i8o is an I/O card in FMC form-factor. This card uses a
low-pint count (LPC) connector.
It's 10 inputs use fast differential comparators (propagation delay < 1
ns) with 12-bit DAC to set references. The 8 outputs are LVTTL level.
Other FMC projects and the FMC standard are described in "FMC Projects:/project/fmc-projects" .
Main features
* FMC low-pin count (LPC)
- Supported Vadj| 1.8V and 2.5V
- FMC connectivity: all 34 differential pairs connected, I2C
* Inputs - 10 x high speed inputs and comparators
- Programmable threshold: 5V to -5V using DAC with 5mV precision
- Input bandwidth: 350MHz
- Selectable: High-impedance or 50 Ohm
* Outputs: - 8 x digital LVTTL
- MAX9122 as LVDS 100Ohm integrated buffer and LVC
- 2 x isolated contact for PLC fail-safe functionality
* Comparators - 5 x LMH7324 Quad high speed comparator
- Number of comparators: 20 (2 per input channel)
- Voltage references: 20 (1 per comparator)
- Communication with FPGA: LVDS, 1 pair per channel
* ID, memory and impedance - Unique 64-bit identifier (DS2411R+), 1.8V and one-wire compatible
- 64 kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
- Input impedance changed with I2C expander (TCA6416APWR)
* 8-layer PCB
Project information
- Documentation of the first prototype is available here
- Second draw schematics
- First draw schematics
- Hysteresis calculation and simulation
- Software
- Frequently Asked Questions
- Users
Contacts
Commercial producers
- none yet
Project
- Simon Andre J Uyttenhove <simon.uyttenhove@cern.ch>
- Pieter Van Trappen <pieter.van.trappen@cern.ch>
Project Status
Date | Event |
02-06-2015 | First ideas for the I/O card. |
27-07-2015 | Creation of Open Hardware project, selection of connector and fast comparator. |
04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice |
08-09-2015 | First schematics and reviewing process |
22-09-2015 | First schematics improved |
06-11-2015 | Review with BE-CO, available here Review-first-draw (Corrections-after-Review-first-draw) |
24-11-2015 | Second draw of the schematics available |
16-11-2015 | Schematics sent to CERN design office for PCB layout and production of two samples |
26-11-2015 | Review of the PCB-layout from BE/CO department |
27-11-2015 | PCB prototypes in production |
21-03-2016 | VDHL code writing process started |
06-04-2016 | Reception of PCB samples and tests |
04 April 2016