pax_global_header 0000666 0000000 0000000 00000000064 13451063467 0014523 g ustar 00root root 0000000 0000000 52 comment=6c4814e056aebec42382e03158731078f0b5c0f1
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/ 0000775 0000000 0000000 00000000000 13451063467 0021150 5 ustar 00root root 0000000 0000000 fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/README.md 0000664 0000000 0000000 00000000000 13451063467 0022415 0 ustar 00root root 0000000 0000000 fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/ 0000775 0000000 0000000 00000000000 13451063467 0022620 5 ustar 00root root 0000000 0000000 fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/ 0000775 0000000 0000000 00000000000 13451063467 0024455 5 ustar 00root root 0000000 0000000 fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/Manifest.py 0000664 0000000 0000000 00000000113 13451063467 0026570 0 ustar 00root root 0000000 0000000 files = ["wrsw_dio_wb.vhd",
"wrsw_dio.vhd",
"dummy_time.vhd" ]
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/dummy_time.vhd 0000775 0000000 0000000 00000006510 13451063467 0027336 0 ustar 00root root 0000000 0000000 -------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n: in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond: std_logic;
signal init_time: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
oneSecond <= '0';
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others=>'0');
end if;
if(Tm_cycles_Aux = MaxCountcycles1) then
OneSecond <= '1';
else
OneSecond <= '0';
end if;
init_time <= '1';
end if;
end process P_CountTM_cycles;
P_CountTM_UTC:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others=>'0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond='1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others=>'0');
end if;
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
end Behavioral;
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/wrsw_dio.vhd 0000775 0000000 0000000 00000074624 13451063467 0027035 0 ustar 00root root 0000000 0000000 -------------------------------------------------------------------------------
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wrsw_dio.vhd
-- Author : Rafael Rodriguez, Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
-- Last update: 2012-03-20
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: The DIO core allows configuration of each one of the 5 channels of
-- the DIO mezzanine as input or output. For inputs, it provides an accurate seconds
-- time stamp (using seconds from the WRPC, not shown in the diagram) and
-- a host (PCIe) interrupt via the IRQ Gen block. For outputs, it allows the user
-- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately.
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-- 2012-07-05 0.3 Javier.d Midified wrsw_dio_wb, modified interface
-------------------------------------------------------------------------------
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
entity wrsw_dio is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- Debug signals for chipscope
TRIG0 : out std_logic_vector(31 downto 0);
TRIG1 : out std_logic_vector(31 downto 0);
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
-- wb_irq_data_fifo_o : out std_logic -- T.B.DELETED
);
end wrsw_dio;
architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
-- component dummy_time is
-- port(
-- clk_sys : in std_logic;
-- rst_n : in std_logic;
-- tm_utc : out std_logic_vector(39 downto 0);
-- tm_cycles : out std_logic_vector(27 downto 0));
-- end component;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
-- output when the seconds time passed to it through a vector equals a
-- pre-programmed seconds time.
-------------------------------------------------------------------------------
component pulse_gen is
generic (
g_ref_clk_rate : integer := 125000000
);
port (
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_o : out std_logic; -- pulse output
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't
-- produce pulses and keep trig_ready_o line permamaently active)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
-- 1: input is ready to accept next trigger time tag
trig_ready_o : out std_logic;
-- time at which the pulse will be produced + a single-cycle strobe to
-- latch it in
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- PULSE STAMPER which associates a time-tag with an asyncrhonous
-- input pulse.
-------------------------------------------------------------------------------
component pulse_stamper is
generic (
-- reference clock frequency
g_ref_clk_rate : integer := 125000000
);
port(
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_a_i : in std_logic; -- pulses to be stamped
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_seconds_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
tag_utc_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_seconds_o and tag_cycles_o
tag_valid_p1_o : out std_logic
);
end component;
component wrsw_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_WB_SLAVES_DIO : integer := 4;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal gpio_out : std_logic_vector(31 downto 0);
signal gpio_in : std_logic_vector(31 downto 0);
signal gpio_oen : std_logic_vector(31 downto 0);
signal onewire_en : std_logic;
signal onewire_pwren : std_logic;
signal scl_pad_in, scl_pad_out, scl_pad_oen : std_logic;
signal sda_pad_in, sda_pad_out, sda_pad_oen : std_logic;
-- Pulse generator trigger registers signals
type t_seconds_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_cycles_array is array (4 downto 0) of std_logic_vector (27 downto 0);
signal trig_seconds : t_seconds_array;
signal trig_cycles : t_cycles_array;
signal trig_valid_p1 : std_logic_vector (4 downto 0);
signal trig_ready : std_logic_vector (4 downto 0);
signal tag_seconds : t_seconds_array;
signal tag_cycles : t_cycles_array;
signal tag_valid_p1 : std_logic_vector (4 downto 0);
-- FIFO signals
signal dio_tsf_wr_req : std_logic_vector (4 downto 0);
signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
signal dio_tsf_wr_empty : std_logic_vector (4 downto 0);
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_cycles : t_cycles_array;
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
-- DEBUG SIGNALS FOR USING seconds time values from dummy_time instead WRPC
signal tm_seconds : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
-- WB Crossbar
constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000000", -- ONEWIRE
1 => x"00000100", -- I2C
2 => x"00000200", -- GPIO
3 => x"00000300"); -- PULSE GEN & STAMPER
constant c_cfg_base_mask : t_wishbone_address_array(3 downto 0) :=
(0 => x"00000f00",
1 => x"00000f00",
2 => x"00000f00",
3 => x"00000f00");
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
-- DIO related signals
signal dio_monost : std_logic_vector(4 downto 0);
signal dio_prog : std_logic_vector(4 downto 0);
signal dio_puls_inmed : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- rtl
-------------------------------------------------------------------------------
begin
-- Dummy counter for simulationg WRPC seconds time
-- U_dummy: dummy_time
-- port map(
-- clk_sys => clk_ref_i,
-- rst_n => rst_n_i,
-- tm_utc => tm_utc,
-- tm_cycles => tm_cycles
-- );
------------------------------------------------------------------------------
-- GEN AND STAMPER
------------------------------------------------------------------------------
gen_pulse_modules : for i in 0 to 4 generate
U_pulse_gen : pulse_gen
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_prog(i),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(i),
trig_utc_i => trig_seconds(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i));
U_pulse_stamper : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => dio_in_i(i),
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc, --tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tag_utc_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_p1_o => tag_valid_p1(i));
end generate gen_pulse_modules;
------------------------------------------------------------------------------
-- WB ONEWIRE MASTER
------------------------------------------------------------------------------
U_Onewire : xwb_onewire_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ports => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(0),
slave_o => cbar_master_in(0),
desc_o => open,
owr_pwren_o(0) => onewire_pwren,
owr_en_o(0) => onewire_en,
owr_i(0) => dio_onewire_b);
dio_onewire_b <= '0' when onewire_en = '1' else 'Z';
------------------------------------------------------------------------------
-- WB I2C MASTER
------------------------------------------------------------------------------
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(1),
slave_o => cbar_master_in(1),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
dio_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
dio_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= dio_scl_b;
sda_pad_in <= dio_sda_b;
dio_ga_o<="00"; -- Innused because SPEC boards have these fmc signals to ground
------------------------------------------------------------------------------
-- WB GPIO PORT
------------------------------------------------------------------------------
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => 32,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(2),
slave_o => cbar_master_in(2),
desc_o => open,
gpio_b => open,
gpio_out_o => gpio_out,
gpio_in_i => gpio_in,
gpio_oen_o => gpio_oen);
------------------------------------------------------------------------------
-- WB Crossbar
------------------------------------------------------------------------------
WB_INTERCON : xwb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 4,
g_registered => true,
-- Address of the slaves connected
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Master connections
slave_i(0) => slave_i,
slave_o(0) => slave_o,
-- Slave conenctions
master_i => cbar_master_in,
master_o => cbar_master_out
);
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
dio_monost(i) <= '1' when dio_puls_inmed(i) = '1' else dio_prog(i);
dio_out_o(i) <= dio_monost(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_oe_n_o(i) <= gpio_out(4*i+1);
dio_term_en_o(i) <= gpio_out(4*i+2);
end generate gen_pio_assignment;
dio_led_bot_o <= gpio_out(28);
dio_led_top_o <= gpio_out(27);
gpio_in(29) <= dio_clk_i;
dio_sdn_ck_n_o <= gpio_out(30);
dio_sdn_n_o <= gpio_out(31);
------------------------------------------------------------------------------
-- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
------------------------------------------------------------------------------
U_seconds_wbslave : wrsw_dio_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => cbar_master_out(3).adr(7 downto 2), -- only word acesses are available
wb_dat_i => cbar_master_out(3).dat,
wb_dat_o => cbar_master_in(3).dat,
wb_cyc_i => cbar_master_out(3).cyc,
wb_sel_i => cbar_master_out(3).sel,
wb_stb_i => cbar_master_out(3).stb,
wb_we_i => cbar_master_out(3).we,
wb_ack_o => cbar_master_in(3).ack,
wb_stall_o => cbar_master_in(3).stall,
wb_int_o => cbar_master_in(3).int,--wb_irq_data_fifo_o, --slave_o.int,
clk_asyn_i => clk_ref_i,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
dio_tsf0_wr_full_o => dio_tsf_wr_full(0),
dio_tsf0_wr_empty_o => dio_tsf_wr_empty(0),
dio_tsf0_tag_seconds_i => dio_tsf_tag_seconds(0)(31 downto 0),
dio_tsf0_tag_secondsh_i => dio_tsf_tag_seconds(0)(39 downto 32),
dio_tsf0_tag_cycles_i => dio_tsf_tag_cycles(0),
irq_nempty_0_i => irq_nempty(0),
dio_tsf1_wr_req_i => dio_tsf_wr_req(1),
dio_tsf1_wr_full_o => dio_tsf_wr_full(1),
dio_tsf1_wr_empty_o => dio_tsf_wr_empty(1),
dio_tsf1_tag_seconds_i => dio_tsf_tag_seconds(1)(31 downto 0),
dio_tsf1_tag_secondsh_i => dio_tsf_tag_seconds(1)(39 downto 32),
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
dio_tsf2_wr_full_o => dio_tsf_wr_full(2),
dio_tsf2_wr_empty_o => dio_tsf_wr_empty(2),
dio_tsf2_tag_seconds_i => dio_tsf_tag_seconds(2)(31 downto 0),
dio_tsf2_tag_secondsh_i => dio_tsf_tag_seconds(2)(39 downto 32),
dio_tsf2_tag_cycles_i => dio_tsf_tag_cycles(2),
irq_nempty_2_i => irq_nempty(2),
dio_tsf3_wr_req_i => dio_tsf_wr_req(3),
dio_tsf3_wr_full_o => dio_tsf_wr_full(3),
dio_tsf3_wr_empty_o => dio_tsf_wr_empty(3),
dio_tsf3_tag_seconds_i => dio_tsf_tag_seconds(3)(31 downto 0),
dio_tsf3_tag_secondsh_i => dio_tsf_tag_seconds(3)(39 downto 32),
dio_tsf3_tag_cycles_i => dio_tsf_tag_cycles(3),
irq_nempty_3_i => irq_nempty(3),
dio_tsf4_wr_req_i => dio_tsf_wr_req(4),
dio_tsf4_wr_full_o => dio_tsf_wr_full(4),
dio_tsf4_wr_empty_o => dio_tsf_wr_empty(4),
dio_tsf4_tag_seconds_i => dio_tsf_tag_seconds(4)(31 downto 0),
dio_tsf4_tag_secondsh_i => dio_tsf_tag_seconds(4)(39 downto 32),
dio_tsf4_tag_cycles_i => dio_tsf_tag_cycles(4),
irq_nempty_4_i => irq_nempty(4),
dio_trig0_seconds_o => trig_seconds(0)(31 downto 0),
dio_trigh0_seconds_o => trig_seconds(0)(39 downto 32),
dio_cyc0_cyc_o => trig_cycles(0),
dio_trig1_seconds_o => trig_seconds(1)(31 downto 0),
dio_trigh1_seconds_o => trig_seconds(1)(39 downto 32),
dio_cyc1_cyc_o => trig_cycles(1),
dio_trig2_seconds_o => trig_seconds(2)(31 downto 0),
dio_trigh2_seconds_o => trig_seconds(2)(39 downto 32),
dio_cyc2_cyc_o => trig_cycles(2),
dio_trig3_seconds_o => trig_seconds(3)(31 downto 0),
dio_trigh3_seconds_o => trig_seconds(3)(39 downto 32),
dio_cyc3_cyc_o => trig_cycles(3),
dio_trig4_seconds_o => trig_seconds(4)(31 downto 0),
dio_trigh4_seconds_o => trig_seconds(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4),
dio_out_mode_o => dio_out_mode,
dio_latch_time_ch0_o => trig_valid_p1(0),
dio_latch_time_ch1_o => trig_valid_p1(1),
dio_latch_time_ch2_o => trig_valid_p1(2),
dio_latch_time_ch3_o => trig_valid_p1(3),
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_trig_rdy_i => trig_ready,
dio_puls_inmed_pul_inm_0_o => dio_puls_inmed(0),
dio_puls_inmed_pul_inm_1_o => dio_puls_inmed(1),
dio_puls_inmed_pul_inm_2_o => dio_puls_inmed(2),
dio_puls_inmed_pul_inm_3_o => dio_puls_inmed(3),
dio_puls_inmed_pul_inm_4_o => dio_puls_inmed(4)
);
-- seconds timestamped FIFO-no-empty interrupts
irq_fifos : for i in 0 to 4 generate
irq_nempty(i) <= not dio_tsf_wr_empty(i);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dio_tsf_wr_req(i) <= '0';
dio_tsf_tag_seconds(i) <= (others => '0');
dio_tsf_tag_cycles(i) <= (others => '0');
else
if ((tag_valid_p1(i) = '1') AND (dio_tsf_wr_full(i)='0')) then
dio_tsf_wr_req(i) <='1';
dio_tsf_tag_seconds(i) <=tag_seconds(i);
dio_tsf_tag_cycles(i) <=tag_cycles(i);
else
dio_tsf_wr_req(i) <='0';
end if;
end if;
end if;
end process;
end generate irq_fifos;
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
-- TRIG0 <= tag_utc(0)(31 downto 0);
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
end rtl;
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/wrsw_dio.wb 0000775 0000000 0000000 00000037071 13451063467 0026657 0 ustar 00root root 0000000 0000000 -- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "FMC-DIO-5chttla";
prefix="dio";
hdl_entity="wrsw_dio_wb";
---------------------------------------
-- FIFOS FOR INPUT EVENT TIME STAMPING
---------------------------------------
-- CHANNEL 0 INPUT FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf0";
name = "Timestamp FIFO 0";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - seconds time\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "seconds time (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
};
-- CHANNEL 0 INTERRUPTS
irq {
name = "dio fifo not-empty 0";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_0";
trigger = LEVEL_1;
};
-- CHANNEL 1 INPUT FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf1";
name = "Timestamp FIFO 1";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
};
-- CHANNEL 1 INTERRUPTS
irq {
name = "dio fifo not-empty 1";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_1";
trigger = LEVEL_1;
};
-- CHANNEL 2 INPUT FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf2";
name = "Timestamp FIFO 2";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
};
-- CHANNEL 2 INTERRUPTS
irq {
name = "dio fifo not-empty 2";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_2";
trigger = LEVEL_1;
};
-- CHANNEL 3 INPUT FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf3";
name = "Timestamp FIFO 3";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
};
-- CHANNEL 3 INTERRUPTS
irq {
name = "dio fifo not-empty 3";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_3";
trigger = LEVEL_1;
};
-- CHANNEL 4 INPUT FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf4";
name = "Timestamp FIFO 4";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
};
-- CHANNEL 4 INTERRUPTS
irq {
name = "dio fifo not-empty 4";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_4";
trigger = LEVEL_1;
};
-------------------------------------------------
-- REGISTERS FOR OUTPUT EVENT TIME-BASED TRIGGER
-------------------------------------------------
-- DIO CHANNEL 0: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 0 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig0";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 0 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH0";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 0: Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 0 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc0";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 1: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 1 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig1";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 1 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH1";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 1: Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 1 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc1";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 2: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 2 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig2";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 2 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH2";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 2: Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 2 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc2";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 3: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 3 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig3";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 3 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH3";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 3: Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 3 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc3";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 4: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 4 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig4";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 4 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH4";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 4: Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 4 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc4";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Monostable/Programmable output or GPIO selection
reg {
name = "FMC-DIO output configuration register. ";
description = "It allows to choose a Monostable/programmable output or a standard GPIO output.";
prefix = "out";
field {
name = "outmode";
description = "1 for programmable, 0 for GPIO output mode";
prefix = "mode";
type = SLV;
size = 5;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Single-cycle strobe signal to latch the second/cycles values of the programamble output
reg {
name = "Time-programmable output strobe signal";
description = "It is used to latch second/cycles values generation just 1 clock cycle output ";
prefix = "latch";
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch0";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch1";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch2";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch3";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch4";
type = MONOSTABLE;
};
};
-- seconds trigger ready value. Readable-writable the bus, writable from the device.
reg {
name = "FMC-DIO seconds-based trigger is ready to accept a new trigger generation request";
description = "ready state, waiting new trigger commands for dio output.";
prefix = "trig";
field {
name = "trig_rdy field";
description = "TBD";
prefix = "rdy";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Pulse generator.
reg {
name = "Pulse generate immediately";
description = "It is used to generate a pulse immediately";
prefix = "puls_inmed";
field {
name = "pulse_gen_now_0";
description = "It generates a pulse";
prefix = "pul_inm_0";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_1";
description = "It generates a pulse";
prefix = "pul_inm_1";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_2";
description = "It generates a pulse";
prefix = "pul_inm_2";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_3";
description = "It generates a pulse";
prefix = "pul_inm_3";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_4";
description = "It generates a pulse";
prefix = "pul_inm_4";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
};
};
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/wrsw_dio_wb.htm 0000664 0000000 0000000 00000531601 13451063467 0027522 0 ustar 00root root 0000000 0000000
wrsw_dio_wb
wrsw_dio_wb
FMC-DIO-5chttla
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. fmc-dio 0 seconds-based trigger for pulse generation
3.2. fmc-dio 0 seconds-based trigger for pulse generation
3.3. fmc-dio 0 cycles to trigger a pulse generation
3.4. fmc-dio 1 seconds-based trigger for pulse generation
3.5. fmc-dio 1 seconds-based trigger for pulse generation
3.6. fmc-dio 1 cycles to trigger a pulse generation
3.7. fmc-dio 2 seconds-based trigger for pulse generation
3.8. fmc-dio 2 seconds-based trigger for pulse generation
3.9. fmc-dio 2 cycles to trigger a pulse generation
3.10. fmc-dio 3 seconds-based trigger for pulse generation
3.11. fmc-dio 3 seconds-based trigger for pulse generation
3.12. fmc-dio 3 cycles to trigger a pulse generation
3.13. fmc-dio 4 seconds-based trigger for pulse generation
3.14. fmc-dio 4 seconds-based trigger for pulse generation
3.15. fmc-dio 4 cycles to trigger a pulse generation
3.16. FMC-DIO output configuration register.
3.17. Time-programmable output strobe signal
3.18. FMC-DIO seconds-based trigger is ready to accept a new trigger generation request
3.19. Pulse generate immediately
3.20. Interrupt disable register
3.21. Interrupt enable register
3.22. Interrupt mask register
3.23. Interrupt status register
3.24. FIFO 'Timestamp FIFO 0' data output register 0
3.25. FIFO 'Timestamp FIFO 0' data output register 1
3.26. FIFO 'Timestamp FIFO 0' data output register 2
3.27. FIFO 'Timestamp FIFO 0' control/status register
3.28. FIFO 'Timestamp FIFO 1' data output register 0
3.29. FIFO 'Timestamp FIFO 1' data output register 1
3.30. FIFO 'Timestamp FIFO 1' data output register 2
3.31. FIFO 'Timestamp FIFO 1' control/status register
3.32. FIFO 'Timestamp FIFO 2' data output register 0
3.33. FIFO 'Timestamp FIFO 2' data output register 1
3.34. FIFO 'Timestamp FIFO 2' data output register 2
3.35. FIFO 'Timestamp FIFO 2' control/status register
3.36. FIFO 'Timestamp FIFO 3' data output register 0
3.37. FIFO 'Timestamp FIFO 3' data output register 1
3.38. FIFO 'Timestamp FIFO 3' data output register 2
3.39. FIFO 'Timestamp FIFO 3' control/status register
3.40. FIFO 'Timestamp FIFO 4' data output register 0
3.41. FIFO 'Timestamp FIFO 4' data output register 1
3.42. FIFO 'Timestamp FIFO 4' data output register 2
3.43. FIFO 'Timestamp FIFO 4' control/status register
5. Interrupts
5.1. dio fifo not-empty 0
5.2. dio fifo not-empty 1
5.3. dio fifo not-empty 2
5.4. dio fifo not-empty 3
5.5. dio fifo not-empty 4
→
|
rst_n_i
|
|
Timestamp FIFO 0:
|
|
→
|
clk_sys_i
|
|
dio_tsf0_wr_req_i
|
←
|
⇒
|
wb_adr_i[5:0]
|
|
dio_tsf0_wr_full_o
|
→
|
⇒
|
wb_dat_i[31:0]
|
|
dio_tsf0_wr_empty_o
|
→
|
⇐
|
wb_dat_o[31:0]
|
|
dio_tsf0_tag_seconds_i[31:0]
|
⇐
|
→
|
wb_cyc_i
|
|
dio_tsf0_tag_secondsh_i[7:0]
|
⇐
|
⇒
|
wb_sel_i[3:0]
|
|
dio_tsf0_tag_cycles_i[27:0]
|
⇐
|
→
|
wb_stb_i
|
|
|
|
→
|
wb_we_i
|
|
dio fifo not-empty 0:
|
|
←
|
wb_ack_o
|
|
irq_nempty_0_i
|
←
|
←
|
wb_stall_o
|
|
|
|
←
|
wb_int_o
|
|
Timestamp FIFO 1:
|
|
|
|
|
dio_tsf1_wr_req_i
|
←
|
|
|
|
dio_tsf1_wr_full_o
|
→
|
|
|
|
dio_tsf1_wr_empty_o
|
→
|
|
|
|
dio_tsf1_tag_seconds_i[31:0]
|
⇐
|
|
|
|
dio_tsf1_tag_secondsh_i[7:0]
|
⇐
|
|
|
|
dio_tsf1_tag_cycles_i[27:0]
|
⇐
|
|
|
|
|
|
|
|
|
dio fifo not-empty 1:
|
|
|
|
|
irq_nempty_1_i
|
←
|
|
|
|
|
|
|
|
|
Timestamp FIFO 2:
|
|
|
|
|
dio_tsf2_wr_req_i
|
←
|
|
|
|
dio_tsf2_wr_full_o
|
→
|
|
|
|
dio_tsf2_wr_empty_o
|
→
|
|
|
|
dio_tsf2_tag_seconds_i[31:0]
|
⇐
|
|
|
|
dio_tsf2_tag_secondsh_i[7:0]
|
⇐
|
|
|
|
dio_tsf2_tag_cycles_i[27:0]
|
⇐
|
|
|
|
|
|
|
|
|
dio fifo not-empty 2:
|
|
|
|
|
irq_nempty_2_i
|
←
|
|
|
|
|
|
|
|
|
Timestamp FIFO 3:
|
|
|
|
|
dio_tsf3_wr_req_i
|
←
|
|
|
|
dio_tsf3_wr_full_o
|
→
|
|
|
|
dio_tsf3_wr_empty_o
|
→
|
|
|
|
dio_tsf3_tag_seconds_i[31:0]
|
⇐
|
|
|
|
dio_tsf3_tag_secondsh_i[7:0]
|
⇐
|
|
|
|
dio_tsf3_tag_cycles_i[27:0]
|
⇐
|
|
|
|
|
|
|
|
|
dio fifo not-empty 3:
|
|
|
|
|
irq_nempty_3_i
|
←
|
|
|
|
|
|
|
|
|
Timestamp FIFO 4:
|
|
|
|
|
dio_tsf4_wr_req_i
|
←
|
|
|
|
dio_tsf4_wr_full_o
|
→
|
|
|
|
dio_tsf4_wr_empty_o
|
→
|
|
|
|
dio_tsf4_tag_seconds_i[31:0]
|
⇐
|
|
|
|
dio_tsf4_tag_secondsh_i[7:0]
|
⇐
|
|
|
|
dio_tsf4_tag_cycles_i[27:0]
|
⇐
|
|
|
|
|
|
|
|
|
dio fifo not-empty 4:
|
|
|
|
|
irq_nempty_4_i
|
←
|
|
|
|
|
|
|
|
|
fmc-dio 0 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trig0_seconds_o[31:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 0 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trigh0_seconds_o[7:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 0 cycles to trigger a pulse generation:
|
|
|
|
|
dio_cyc0_cyc_o[27:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 1 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trig1_seconds_o[31:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 1 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trigh1_seconds_o[7:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 1 cycles to trigger a pulse generation:
|
|
|
|
|
dio_cyc1_cyc_o[27:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 2 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trig2_seconds_o[31:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 2 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trigh2_seconds_o[7:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 2 cycles to trigger a pulse generation:
|
|
|
|
|
dio_cyc2_cyc_o[27:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 3 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trig3_seconds_o[31:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 3 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trigh3_seconds_o[7:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 3 cycles to trigger a pulse generation:
|
|
|
|
|
dio_cyc3_cyc_o[27:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 4 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trig4_seconds_o[31:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 4 seconds-based trigger for pulse generation:
|
|
|
|
|
dio_trigh4_seconds_o[7:0]
|
⇒
|
|
|
|
|
|
|
|
|
fmc-dio 4 cycles to trigger a pulse generation:
|
|
|
|
|
dio_cyc4_cyc_o[27:0]
|
⇒
|
|
|
|
|
|
|
|
|
FMC-DIO output configuration register. :
|
|
|
|
|
dio_out_mode_o[4:0]
|
⇒
|
|
|
|
|
|
|
|
|
Time-programmable output strobe signal:
|
|
|
|
|
dio_latch_time_ch0_o
|
→
|
|
|
|
dio_latch_time_ch1_o
|
→
|
|
|
|
dio_latch_time_ch2_o
|
→
|
|
|
|
dio_latch_time_ch3_o
|
→
|
|
|
|
dio_latch_time_ch4_o
|
→
|
|
|
|
|
|
|
|
|
FMC-DIO seconds-based trigger is ready to accept a new trigger generation request:
|
|
|
|
|
dio_trig_rdy_i[4:0]
|
⇐
|
|
|
|
|
|
|
|
|
Pulse generate immediately:
|
|
|
|
|
dio_puls_inmed_pul_inm_0_o
|
→
|
|
|
|
dio_puls_inmed_pul_inm_1_o
|
→
|
|
|
|
dio_puls_inmed_pul_inm_2_o
|
→
|
|
|
|
dio_puls_inmed_pul_inm_3_o
|
→
|
|
|
|
dio_puls_inmed_pul_inm_4_o
|
→
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 0' data output register 0:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 0' data output register 1:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 0' data output register 2:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 1' data output register 0:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 1' data output register 1:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 1' data output register 2:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 2' data output register 0:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 2' data output register 1:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 2' data output register 2:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 3' data output register 0:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 3' data output register 1:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 3' data output register 2:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 4' data output register 0:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 4' data output register 1:
|
|
|
|
|
|
|
|
|
|
FIFO 'Timestamp FIFO 4' data output register 2:
|
|
HW prefix:
|
dio_trig0
|
HW address:
|
0x0
|
C prefix:
|
TRIG0
|
C offset:
|
0x0
|
trigger seconds value for dio output (LSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
TBD
HW prefix:
|
dio_trigh0
|
HW address:
|
0x1
|
C prefix:
|
TRIGH0
|
C offset:
|
0x4
|
trigger seconds value for dio output (MSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
Number of seconds
HW prefix:
|
dio_cyc0
|
HW address:
|
0x2
|
C prefix:
|
CYC0
|
C offset:
|
0x8
|
sub-second accuracy values (clock cycles) to trigger dio output channels.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
CYC[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
CYC[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
CYC[15:8]
|
|
|
|
|
|
|
|
-
CYC
[read/write]: cycles field
Number of cycles in one second (depends on current clock frequency)
HW prefix:
|
dio_trig1
|
HW address:
|
0x3
|
C prefix:
|
TRIG1
|
C offset:
|
0xc
|
trigger seconds value for dio output (LSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
TBD
HW prefix:
|
dio_trigh1
|
HW address:
|
0x4
|
C prefix:
|
TRIGH1
|
C offset:
|
0x10
|
trigger seconds value for dio output (MSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
Number of seconds
HW prefix:
|
dio_cyc1
|
HW address:
|
0x5
|
C prefix:
|
CYC1
|
C offset:
|
0x14
|
sub-second accuracy values (clock cycles) to trigger dio output channels.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
CYC[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
CYC[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
CYC[15:8]
|
|
|
|
|
|
|
|
-
CYC
[read/write]: cycles field
Number of cycles in one second (depends on current clock frequency)
HW prefix:
|
dio_trig2
|
HW address:
|
0x6
|
C prefix:
|
TRIG2
|
C offset:
|
0x18
|
trigger seconds value for dio output (LSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
TBD
HW prefix:
|
dio_trigh2
|
HW address:
|
0x7
|
C prefix:
|
TRIGH2
|
C offset:
|
0x1c
|
trigger seconds value for dio output (MSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
Number of seconds
HW prefix:
|
dio_cyc2
|
HW address:
|
0x8
|
C prefix:
|
CYC2
|
C offset:
|
0x20
|
sub-second accuracy values (clock cycles) to trigger dio output channels.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
CYC[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
CYC[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
CYC[15:8]
|
|
|
|
|
|
|
|
-
CYC
[read/write]: cycles field
Number of cycles in one second (depends on current clock frequency)
HW prefix:
|
dio_trig3
|
HW address:
|
0x9
|
C prefix:
|
TRIG3
|
C offset:
|
0x24
|
trigger seconds value for dio output (LSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
TBD
HW prefix:
|
dio_trigh3
|
HW address:
|
0xa
|
C prefix:
|
TRIGH3
|
C offset:
|
0x28
|
trigger seconds value for dio output (MSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
Number of seconds
HW prefix:
|
dio_cyc3
|
HW address:
|
0xb
|
C prefix:
|
CYC3
|
C offset:
|
0x2c
|
sub-second accuracy values (clock cycles) to trigger dio output channels.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
CYC[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
CYC[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
CYC[15:8]
|
|
|
|
|
|
|
|
-
CYC
[read/write]: cycles field
Number of cycles in one second (depends on current clock frequency)
HW prefix:
|
dio_trig4
|
HW address:
|
0xc
|
C prefix:
|
TRIG4
|
C offset:
|
0x30
|
trigger seconds value for dio output (LSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
TBD
HW prefix:
|
dio_trigh4
|
HW address:
|
0xd
|
C prefix:
|
TRIGH4
|
C offset:
|
0x34
|
trigger seconds value for dio output (MSB).
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
SECONDS[7:0]
|
|
|
|
|
|
|
|
-
SECONDS
[read/write]: seconds field
Number of seconds
HW prefix:
|
dio_cyc4
|
HW address:
|
0xe
|
C prefix:
|
CYC4
|
C offset:
|
0x38
|
sub-second accuracy values (clock cycles) to trigger dio output channels.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
CYC[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
CYC[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
CYC[15:8]
|
|
|
|
|
|
|
|
-
CYC
[read/write]: cycles field
Number of cycles in one second (depends on current clock frequency)
HW prefix:
|
dio_out
|
HW address:
|
0xf
|
C prefix:
|
OUT
|
C offset:
|
0x3c
|
It allows to choose a Monostable/programmable output or a standard GPIO output.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
MODE[4:0]
|
|
|
|
|
-
MODE
[read/write]: outmode
1 for programmable, 0 for GPIO output mode
HW prefix:
|
dio_latch
|
HW address:
|
0x10
|
C prefix:
|
LATCH
|
C offset:
|
0x40
|
It is used to latch second/cycles values generation just 1 clock cycle output
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
TIME_CH4
|
TIME_CH3
|
TIME_CH2
|
TIME_CH1
|
TIME_CH0
|
-
TIME_CH0
[write-only]: Sincle-cycle strobe
It generates a one-clock cycle pulse for programmable time latching
-
TIME_CH1
[write-only]: Sincle-cycle strobe
It generates a one-clock cycle pulse for programmable time latching
-
TIME_CH2
[write-only]: Sincle-cycle strobe
It generates a one-clock cycle pulse for programmable time latching
-
TIME_CH3
[write-only]: Sincle-cycle strobe
It generates a one-clock cycle pulse for programmable time latching
-
TIME_CH4
[write-only]: Sincle-cycle strobe
It generates a one-clock cycle pulse for programmable time latching
HW prefix:
|
dio_trig
|
HW address:
|
0x11
|
C prefix:
|
TRIG
|
C offset:
|
0x44
|
ready state, waiting new trigger commands for dio output.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
RDY[4:0]
|
|
|
|
|
-
RDY
[read-only]: trig_rdy field
TBD
HW prefix:
|
dio_puls_inmed
|
HW address:
|
0x12
|
C prefix:
|
PULS_INMED
|
C offset:
|
0x48
|
It is used to generate a pulse immediately
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
PUL_INM_4
|
PUL_INM_3
|
PUL_INM_2
|
PUL_INM_1
|
PUL_INM_0
|
-
PUL_INM_0
[write-only]: pulse_gen_now_0
It generates a pulse
-
PUL_INM_1
[write-only]: pulse_gen_now_1
It generates a pulse
-
PUL_INM_2
[write-only]: pulse_gen_now_2
It generates a pulse
-
PUL_INM_3
[write-only]: pulse_gen_now_3
It generates a pulse
-
PUL_INM_4
[write-only]: pulse_gen_now_4
It generates a pulse
HW prefix:
|
dio_eic_idr
|
HW address:
|
0x18
|
C prefix:
|
EIC_IDR
|
C offset:
|
0x60
|
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
NEMPTY_4
|
NEMPTY_3
|
NEMPTY_2
|
NEMPTY_1
|
NEMPTY_0
|
-
NEMPTY_0
[write-only]: dio fifo not-empty 0
write 1: disable interrupt 'dio fifo not-empty 0'
write 0: no effect
-
NEMPTY_1
[write-only]: dio fifo not-empty 1
write 1: disable interrupt 'dio fifo not-empty 1'
write 0: no effect
-
NEMPTY_2
[write-only]: dio fifo not-empty 2
write 1: disable interrupt 'dio fifo not-empty 2'
write 0: no effect
-
NEMPTY_3
[write-only]: dio fifo not-empty 3
write 1: disable interrupt 'dio fifo not-empty 3'
write 0: no effect
-
NEMPTY_4
[write-only]: dio fifo not-empty 4
write 1: disable interrupt 'dio fifo not-empty 4'
write 0: no effect
HW prefix:
|
dio_eic_ier
|
HW address:
|
0x19
|
C prefix:
|
EIC_IER
|
C offset:
|
0x64
|
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
NEMPTY_4
|
NEMPTY_3
|
NEMPTY_2
|
NEMPTY_1
|
NEMPTY_0
|
-
NEMPTY_0
[write-only]: dio fifo not-empty 0
write 1: enable interrupt 'dio fifo not-empty 0'
write 0: no effect
-
NEMPTY_1
[write-only]: dio fifo not-empty 1
write 1: enable interrupt 'dio fifo not-empty 1'
write 0: no effect
-
NEMPTY_2
[write-only]: dio fifo not-empty 2
write 1: enable interrupt 'dio fifo not-empty 2'
write 0: no effect
-
NEMPTY_3
[write-only]: dio fifo not-empty 3
write 1: enable interrupt 'dio fifo not-empty 3'
write 0: no effect
-
NEMPTY_4
[write-only]: dio fifo not-empty 4
write 1: enable interrupt 'dio fifo not-empty 4'
write 0: no effect
HW prefix:
|
dio_eic_imr
|
HW address:
|
0x1a
|
C prefix:
|
EIC_IMR
|
C offset:
|
0x68
|
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
NEMPTY_4
|
NEMPTY_3
|
NEMPTY_2
|
NEMPTY_1
|
NEMPTY_0
|
-
NEMPTY_0
[read-only]: dio fifo not-empty 0
read 1: interrupt 'dio fifo not-empty 0' is enabled
read 0: interrupt 'dio fifo not-empty 0' is disabled
-
NEMPTY_1
[read-only]: dio fifo not-empty 1
read 1: interrupt 'dio fifo not-empty 1' is enabled
read 0: interrupt 'dio fifo not-empty 1' is disabled
-
NEMPTY_2
[read-only]: dio fifo not-empty 2
read 1: interrupt 'dio fifo not-empty 2' is enabled
read 0: interrupt 'dio fifo not-empty 2' is disabled
-
NEMPTY_3
[read-only]: dio fifo not-empty 3
read 1: interrupt 'dio fifo not-empty 3' is enabled
read 0: interrupt 'dio fifo not-empty 3' is disabled
-
NEMPTY_4
[read-only]: dio fifo not-empty 4
read 1: interrupt 'dio fifo not-empty 4' is enabled
read 0: interrupt 'dio fifo not-empty 4' is disabled
HW prefix:
|
dio_eic_isr
|
HW address:
|
0x1b
|
C prefix:
|
EIC_ISR
|
C offset:
|
0x6c
|
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
NEMPTY_4
|
NEMPTY_3
|
NEMPTY_2
|
NEMPTY_1
|
NEMPTY_0
|
-
NEMPTY_0
[read/write]: dio fifo not-empty 0
read 1: interrupt 'dio fifo not-empty 0' is pending
read 0: interrupt not pending
write 1: clear interrupt 'dio fifo not-empty 0'
write 0: no effect
-
NEMPTY_1
[read/write]: dio fifo not-empty 1
read 1: interrupt 'dio fifo not-empty 1' is pending
read 0: interrupt not pending
write 1: clear interrupt 'dio fifo not-empty 1'
write 0: no effect
-
NEMPTY_2
[read/write]: dio fifo not-empty 2
read 1: interrupt 'dio fifo not-empty 2' is pending
read 0: interrupt not pending
write 1: clear interrupt 'dio fifo not-empty 2'
write 0: no effect
-
NEMPTY_3
[read/write]: dio fifo not-empty 3
read 1: interrupt 'dio fifo not-empty 3' is pending
read 0: interrupt not pending
write 1: clear interrupt 'dio fifo not-empty 3'
write 0: no effect
-
NEMPTY_4
[read/write]: dio fifo not-empty 4
read 1: interrupt 'dio fifo not-empty 4' is pending
read 0: interrupt not pending
write 1: clear interrupt 'dio fifo not-empty 4'
write 0: no effect
HW prefix:
|
dio_tsf0_r0
|
HW address:
|
0x1c
|
C prefix:
|
TSF0_R0
|
C offset:
|
0x70
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TAG_SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDS[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDS
[read-only]: seconds time
HW prefix:
|
dio_tsf0_r1
|
HW address:
|
0x1d
|
C prefix:
|
TSF0_R1
|
C offset:
|
0x74
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDSH[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDSH
[read-only]: seconds time H
HW prefix:
|
dio_tsf0_r2
|
HW address:
|
0x1e
|
C prefix:
|
TSF0_R2
|
C offset:
|
0x78
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
TAG_CYCLES[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_CYCLES[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_CYCLES[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_CYCLES[7:0]
|
|
|
|
|
|
|
|
-
TAG_CYCLES
[read-only]: Sub-second accuracy
HW prefix:
|
dio_tsf0_csr
|
HW address:
|
0x1f
|
C prefix:
|
TSF0_CSR
|
C offset:
|
0x7c
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
EMPTY
|
FULL
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
USEDW[7:0]
|
|
|
|
|
|
|
|
-
FULL
[read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO 0' is full
0: FIFO is not full
-
EMPTY
[read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO 0' is empty
0: FIFO is not empty
-
USEDW
[read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO 0'
HW prefix:
|
dio_tsf1_r0
|
HW address:
|
0x20
|
C prefix:
|
TSF1_R0
|
C offset:
|
0x80
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TAG_SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDS[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDS
[read-only]: seconds time
HW prefix:
|
dio_tsf1_r1
|
HW address:
|
0x21
|
C prefix:
|
TSF1_R1
|
C offset:
|
0x84
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDSH[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDSH
[read-only]: seconds time H
HW prefix:
|
dio_tsf1_r2
|
HW address:
|
0x22
|
C prefix:
|
TSF1_R2
|
C offset:
|
0x88
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
TAG_CYCLES[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_CYCLES[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_CYCLES[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_CYCLES[7:0]
|
|
|
|
|
|
|
|
-
TAG_CYCLES
[read-only]: Sub-second accuracy
HW prefix:
|
dio_tsf1_csr
|
HW address:
|
0x23
|
C prefix:
|
TSF1_CSR
|
C offset:
|
0x8c
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
EMPTY
|
FULL
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
USEDW[7:0]
|
|
|
|
|
|
|
|
-
FULL
[read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO 1' is full
0: FIFO is not full
-
EMPTY
[read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO 1' is empty
0: FIFO is not empty
-
USEDW
[read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO 1'
HW prefix:
|
dio_tsf2_r0
|
HW address:
|
0x24
|
C prefix:
|
TSF2_R0
|
C offset:
|
0x90
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TAG_SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDS[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDS
[read-only]: seconds time
HW prefix:
|
dio_tsf2_r1
|
HW address:
|
0x25
|
C prefix:
|
TSF2_R1
|
C offset:
|
0x94
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDSH[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDSH
[read-only]: seconds time H
HW prefix:
|
dio_tsf2_r2
|
HW address:
|
0x26
|
C prefix:
|
TSF2_R2
|
C offset:
|
0x98
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
TAG_CYCLES[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_CYCLES[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_CYCLES[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_CYCLES[7:0]
|
|
|
|
|
|
|
|
-
TAG_CYCLES
[read-only]: Sub-second accuracy
HW prefix:
|
dio_tsf2_csr
|
HW address:
|
0x27
|
C prefix:
|
TSF2_CSR
|
C offset:
|
0x9c
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
EMPTY
|
FULL
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
USEDW[7:0]
|
|
|
|
|
|
|
|
-
FULL
[read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO 2' is full
0: FIFO is not full
-
EMPTY
[read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO 2' is empty
0: FIFO is not empty
-
USEDW
[read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO 2'
HW prefix:
|
dio_tsf3_r0
|
HW address:
|
0x28
|
C prefix:
|
TSF3_R0
|
C offset:
|
0xa0
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TAG_SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDS[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDS
[read-only]: seconds time
HW prefix:
|
dio_tsf3_r1
|
HW address:
|
0x29
|
C prefix:
|
TSF3_R1
|
C offset:
|
0xa4
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDSH[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDSH
[read-only]: seconds time H
HW prefix:
|
dio_tsf3_r2
|
HW address:
|
0x2a
|
C prefix:
|
TSF3_R2
|
C offset:
|
0xa8
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
TAG_CYCLES[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_CYCLES[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_CYCLES[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_CYCLES[7:0]
|
|
|
|
|
|
|
|
-
TAG_CYCLES
[read-only]: Sub-second accuracy
HW prefix:
|
dio_tsf3_csr
|
HW address:
|
0x2b
|
C prefix:
|
TSF3_CSR
|
C offset:
|
0xac
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
EMPTY
|
FULL
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
USEDW[7:0]
|
|
|
|
|
|
|
|
-
FULL
[read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO 3' is full
0: FIFO is not full
-
EMPTY
[read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO 3' is empty
0: FIFO is not empty
-
USEDW
[read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO 3'
HW prefix:
|
dio_tsf4_r0
|
HW address:
|
0x2c
|
C prefix:
|
TSF4_R0
|
C offset:
|
0xb0
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TAG_SECONDS[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_SECONDS[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_SECONDS[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDS[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDS
[read-only]: seconds time
HW prefix:
|
dio_tsf4_r1
|
HW address:
|
0x2d
|
C prefix:
|
TSF4_R1
|
C offset:
|
0xb4
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_SECONDSH[7:0]
|
|
|
|
|
|
|
|
-
TAG_SECONDSH
[read-only]: seconds time H
HW prefix:
|
dio_tsf4_r2
|
HW address:
|
0x2e
|
C prefix:
|
TSF4_R2
|
C offset:
|
0xb8
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
TAG_CYCLES[27:24]
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TAG_CYCLES[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TAG_CYCLES[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TAG_CYCLES[7:0]
|
|
|
|
|
|
|
|
-
TAG_CYCLES
[read-only]: Sub-second accuracy
HW prefix:
|
dio_tsf4_csr
|
HW address:
|
0x2f
|
C prefix:
|
TSF4_CSR
|
C offset:
|
0xbc
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
EMPTY
|
FULL
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
USEDW[7:0]
|
|
|
|
|
|
|
|
-
FULL
[read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO 4' is full
0: FIFO is not full
-
EMPTY
[read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO 4' is empty
0: FIFO is not empty
-
USEDW
[read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO 4'
HW prefix:
|
dio_nempty_0
|
C prefix:
|
NEMPTY_0
|
Trigger:
|
high level
|
Interrupt active when dio input FIFO contains any timestamps.
HW prefix:
|
dio_nempty_1
|
C prefix:
|
NEMPTY_1
|
Trigger:
|
high level
|
Interrupt active when dio input FIFO contains any timestamps.
HW prefix:
|
dio_nempty_2
|
C prefix:
|
NEMPTY_2
|
Trigger:
|
high level
|
Interrupt active when dio input FIFO contains any timestamps.
HW prefix:
|
dio_nempty_3
|
C prefix:
|
NEMPTY_3
|
Trigger:
|
high level
|
Interrupt active when dio input FIFO contains any timestamps.
HW prefix:
|
dio_nempty_4
|
C prefix:
|
NEMPTY_4
|
Trigger:
|
high level
|
Interrupt active when dio input FIFO contains any timestamps.
fmc-dio-5chttla-6c4814e056aebec42382e03158731078f0b5c0f1/modules/wrsw_dio/wrsw_dio_wb.vhd 0000664 0000000 0000000 00000215055 13451063467 0027515 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC-DIO-5chttla
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Fri Jun 29 10:14:46 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wrsw_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
);
end wrsw_dio_wb;
architecture syn of wrsw_dio_wb is
signal dio_tsf0_rst_n : std_logic ;
signal dio_tsf0_in_int : std_logic_vector(67 downto 0);
signal dio_tsf0_out_int : std_logic_vector(67 downto 0);
signal dio_tsf0_rdreq_int : std_logic ;
signal dio_tsf0_rdreq_int_d0 : std_logic ;
signal dio_tsf1_rst_n : std_logic ;
signal dio_tsf1_in_int : std_logic_vector(67 downto 0);
signal dio_tsf1_out_int : std_logic_vector(67 downto 0);
signal dio_tsf1_rdreq_int : std_logic ;
signal dio_tsf1_rdreq_int_d0 : std_logic ;
signal dio_tsf2_rst_n : std_logic ;
signal dio_tsf2_in_int : std_logic_vector(67 downto 0);
signal dio_tsf2_out_int : std_logic_vector(67 downto 0);
signal dio_tsf2_rdreq_int : std_logic ;
signal dio_tsf2_rdreq_int_d0 : std_logic ;
signal dio_tsf3_rst_n : std_logic ;
signal dio_tsf3_in_int : std_logic_vector(67 downto 0);
signal dio_tsf3_out_int : std_logic_vector(67 downto 0);
signal dio_tsf3_rdreq_int : std_logic ;
signal dio_tsf3_rdreq_int_d0 : std_logic ;
signal dio_tsf4_rst_n : std_logic ;
signal dio_tsf4_in_int : std_logic_vector(67 downto 0);
signal dio_tsf4_out_int : std_logic_vector(67 downto 0);
signal dio_tsf4_rdreq_int : std_logic ;
signal dio_tsf4_rdreq_int_d0 : std_logic ;
signal dio_trig0_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh0_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig1_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh1_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig2_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh2_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig3_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh3_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_out_mode_int : std_logic_vector(4 downto 0);
signal dio_latch_time_ch0_dly0 : std_logic ;
signal dio_latch_time_ch0_int : std_logic ;
signal dio_latch_time_ch1_dly0 : std_logic ;
signal dio_latch_time_ch1_int : std_logic ;
signal dio_latch_time_ch2_dly0 : std_logic ;
signal dio_latch_time_ch2_int : std_logic ;
signal dio_latch_time_ch3_dly0 : std_logic ;
signal dio_latch_time_ch3_int : std_logic ;
signal dio_latch_time_ch4_dly0 : std_logic ;
signal dio_latch_time_ch4_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_1_int : std_logic ;
signal dio_puls_inmed_pul_inm_1_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_2_int : std_logic ;
signal dio_puls_inmed_pul_inm_2_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_3_int : std_logic ;
signal dio_puls_inmed_pul_inm_3_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_4_int : std_logic ;
signal dio_puls_inmed_pul_inm_4_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync2 : std_logic ;
signal eic_idr_int : std_logic_vector(4 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(4 downto 0);
signal eic_isr_clear_int : std_logic_vector(4 downto 0);
signal eic_isr_status_int : std_logic_vector(4 downto 0);
signal eic_irq_ack_int : std_logic_vector(4 downto 0);
signal eic_isr_write_int : std_logic ;
signal dio_tsf0_full_int : std_logic ;
signal dio_tsf0_empty_int : std_logic ;
signal dio_tsf0_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf1_full_int : std_logic ;
signal dio_tsf1_empty_int : std_logic ;
signal dio_tsf1_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf2_full_int : std_logic ;
signal dio_tsf2_empty_int : std_logic ;
signal dio_tsf2_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf3_full_int : std_logic ;
signal dio_tsf3_empty_int : std_logic ;
signal dio_tsf3_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int : std_logic ;
signal dio_tsf4_empty_int : std_logic ;
signal dio_tsf4_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(4 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dio_trig0_seconds_int <= "00000000000000000000000000000000";
dio_trigh0_seconds_int <= "00000000";
dio_cyc0_cyc_int <= "0000000000000000000000000000";
dio_trig1_seconds_int <= "00000000000000000000000000000000";
dio_trigh1_seconds_int <= "00000000";
dio_cyc1_cyc_int <= "0000000000000000000000000000";
dio_trig2_seconds_int <= "00000000000000000000000000000000";
dio_trigh2_seconds_int <= "00000000";
dio_cyc2_cyc_int <= "0000000000000000000000000000";
dio_trig3_seconds_int <= "00000000000000000000000000000000";
dio_trigh3_seconds_int <= "00000000";
dio_cyc3_cyc_int <= "0000000000000000000000000000";
dio_trig4_seconds_int <= "00000000000000000000000000000000";
dio_trigh4_seconds_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_out_mode_int <= "00000";
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
dio_puls_inmed_pul_inm_0_int <= '0';
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= '0';
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= '0';
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= '0';
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= '0';
dio_puls_inmed_pul_inm_4_int_delay <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
dio_tsf0_rdreq_int <= '0';
dio_tsf1_rdreq_int <= '0';
dio_tsf2_rdreq_int <= '0';
dio_tsf3_rdreq_int <= '0';
dio_tsf4_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
dio_puls_inmed_pul_inm_0_int <= dio_puls_inmed_pul_inm_0_int_delay;
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= dio_puls_inmed_pul_inm_1_int_delay;
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= dio_puls_inmed_pul_inm_2_int_delay;
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= dio_puls_inmed_pul_inm_3_int_delay;
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= dio_puls_inmed_pul_inm_4_int_delay;
dio_puls_inmed_pul_inm_4_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
dio_trig0_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig0_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
dio_trigh0_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh0_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
dio_cyc0_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc0_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
dio_trig1_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig1_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
dio_trigh1_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh1_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
dio_cyc1_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc1_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
dio_trig2_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig2_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
dio_trigh2_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh2_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
dio_cyc2_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc2_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
dio_trig3_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig3_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
dio_trigh3_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh3_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
dio_cyc3_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc3_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
dio_trig4_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig4_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
dio_trigh4_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh4_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
if (wb_we_i = '1') then
dio_cyc4_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc4_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
dio_out_mode_int <= wrdata_reg(4 downto 0);
end if;
rddata_reg(4 downto 0) <= dio_out_mode_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
dio_latch_time_ch0_int <= wrdata_reg(0);
dio_latch_time_ch1_int <= wrdata_reg(1);
dio_latch_time_ch2_int <= wrdata_reg(2);
dio_latch_time_ch3_int <= wrdata_reg(3);
dio_latch_time_ch4_int <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= dio_trig_rdy_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
dio_puls_inmed_pul_inm_0_int <= wrdata_reg(0);
dio_puls_inmed_pul_inm_0_int_delay <= wrdata_reg(0);
dio_puls_inmed_pul_inm_1_int <= wrdata_reg(1);
dio_puls_inmed_pul_inm_1_int_delay <= wrdata_reg(1);
dio_puls_inmed_pul_inm_2_int <= wrdata_reg(2);
dio_puls_inmed_pul_inm_2_int_delay <= wrdata_reg(2);
dio_puls_inmed_pul_inm_3_int <= wrdata_reg(3);
dio_puls_inmed_pul_inm_3_int_delay <= wrdata_reg(3);
dio_puls_inmed_pul_inm_4_int <= wrdata_reg(4);
dio_puls_inmed_pul_inm_4_int_delay <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= eic_imr_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(4 downto 0) <= eic_isr_status_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf0_rdreq_int_d0 = '0') then
dio_tsf0_rdreq_int <= not dio_tsf0_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf0_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf0_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf0_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf0_full_int;
rddata_reg(17) <= dio_tsf0_empty_int;
rddata_reg(7 downto 0) <= dio_tsf0_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf1_rdreq_int_d0 = '0') then
dio_tsf1_rdreq_int <= not dio_tsf1_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf1_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf1_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf1_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf1_full_int;
rddata_reg(17) <= dio_tsf1_empty_int;
rddata_reg(7 downto 0) <= dio_tsf1_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf2_rdreq_int_d0 = '0') then
dio_tsf2_rdreq_int <= not dio_tsf2_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf2_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf2_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf2_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf2_full_int;
rddata_reg(17) <= dio_tsf2_empty_int;
rddata_reg(7 downto 0) <= dio_tsf2_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf3_rdreq_int_d0 = '0') then
dio_tsf3_rdreq_int <= not dio_tsf3_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf3_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf3_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf3_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf3_full_int;
rddata_reg(17) <= dio_tsf3_empty_int;
rddata_reg(7 downto 0) <= dio_tsf3_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf4_rdreq_int_d0 = '0') then
dio_tsf4_rdreq_int <= not dio_tsf4_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf4_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf4_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf4_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf4_full_int;
rddata_reg(17) <= dio_tsf4_empty_int;
rddata_reg(7 downto 0) <= dio_tsf4_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO 0
dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_seconds_i;
dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_secondsh_i;
dio_tsf0_in_int(67 downto 40) <= dio_tsf0_tag_cycles_i;
dio_tsf0_rst_n <= rst_n_i;
dio_tsf0_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf0_wr_req_i,
wr_full_o => dio_tsf0_wr_full_o,
wr_empty_o => dio_tsf0_wr_empty_o,
rd_full_o => dio_tsf0_full_int,
rd_empty_o => dio_tsf0_empty_int,
rd_usedw_o => dio_tsf0_usedw_int,
rd_req_i => dio_tsf0_rdreq_int,
rst_n_i => dio_tsf0_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf0_in_int,
rd_data_o => dio_tsf0_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 1
dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_seconds_i;
dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_secondsh_i;
dio_tsf1_in_int(67 downto 40) <= dio_tsf1_tag_cycles_i;
dio_tsf1_rst_n <= rst_n_i;
dio_tsf1_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf1_wr_req_i,
wr_full_o => dio_tsf1_wr_full_o,
wr_empty_o => dio_tsf1_wr_empty_o,
rd_full_o => dio_tsf1_full_int,
rd_empty_o => dio_tsf1_empty_int,
rd_usedw_o => dio_tsf1_usedw_int,
rd_req_i => dio_tsf1_rdreq_int,
rst_n_i => dio_tsf1_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf1_in_int,
rd_data_o => dio_tsf1_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 2
dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_seconds_i;
dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_secondsh_i;
dio_tsf2_in_int(67 downto 40) <= dio_tsf2_tag_cycles_i;
dio_tsf2_rst_n <= rst_n_i;
dio_tsf2_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf2_wr_req_i,
wr_full_o => dio_tsf2_wr_full_o,
wr_empty_o => dio_tsf2_wr_empty_o,
rd_full_o => dio_tsf2_full_int,
rd_empty_o => dio_tsf2_empty_int,
rd_usedw_o => dio_tsf2_usedw_int,
rd_req_i => dio_tsf2_rdreq_int,
rst_n_i => dio_tsf2_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf2_in_int,
rd_data_o => dio_tsf2_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 3
dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_seconds_i;
dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_secondsh_i;
dio_tsf3_in_int(67 downto 40) <= dio_tsf3_tag_cycles_i;
dio_tsf3_rst_n <= rst_n_i;
dio_tsf3_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf3_wr_req_i,
wr_full_o => dio_tsf3_wr_full_o,
wr_empty_o => dio_tsf3_wr_empty_o,
rd_full_o => dio_tsf3_full_int,
rd_empty_o => dio_tsf3_empty_int,
rd_usedw_o => dio_tsf3_usedw_int,
rd_req_i => dio_tsf3_rdreq_int,
rst_n_i => dio_tsf3_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf3_in_int,
rd_data_o => dio_tsf3_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 4
dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_seconds_i;
dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_secondsh_i;
dio_tsf4_in_int(67 downto 40) <= dio_tsf4_tag_cycles_i;
dio_tsf4_rst_n <= rst_n_i;
dio_tsf4_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf4_wr_req_i,
wr_full_o => dio_tsf4_wr_full_o,
wr_empty_o => dio_tsf4_wr_empty_o,
rd_full_o => dio_tsf4_full_int,
rd_empty_o => dio_tsf4_empty_int,
rd_usedw_o => dio_tsf4_usedw_int,
rd_req_i => dio_tsf4_rdreq_int,
rst_n_i => dio_tsf4_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf4_in_int,
rd_data_o => dio_tsf4_out_int
);
-- seconds field
dio_trig0_seconds_o <= dio_trig0_seconds_int;
-- seconds field
dio_trigh0_seconds_o <= dio_trigh0_seconds_int;
-- cycles field
dio_cyc0_cyc_o <= dio_cyc0_cyc_int;
-- seconds field
dio_trig1_seconds_o <= dio_trig1_seconds_int;
-- seconds field
dio_trigh1_seconds_o <= dio_trigh1_seconds_int;
-- cycles field
dio_cyc1_cyc_o <= dio_cyc1_cyc_int;
-- seconds field
dio_trig2_seconds_o <= dio_trig2_seconds_int;
-- seconds field
dio_trigh2_seconds_o <= dio_trigh2_seconds_int;
-- cycles field
dio_cyc2_cyc_o <= dio_cyc2_cyc_int;
-- seconds field
dio_trig3_seconds_o <= dio_trig3_seconds_int;
-- seconds field
dio_trigh3_seconds_o <= dio_trigh3_seconds_int;
-- cycles field
dio_cyc3_cyc_o <= dio_cyc3_cyc_int;
-- seconds field
dio_trig4_seconds_o <= dio_trig4_seconds_int;
-- seconds field
dio_trigh4_seconds_o <= dio_trigh4_seconds_int;
-- cycles field
dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- outmode
dio_out_mode_o <= dio_out_mode_int;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch0_dly0 <= '0';
dio_latch_time_ch0_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch0_dly0 <= dio_latch_time_ch0_int;
dio_latch_time_ch0_o <= dio_latch_time_ch0_int and (not dio_latch_time_ch0_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch1_dly0 <= '0';
dio_latch_time_ch1_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch1_dly0 <= dio_latch_time_ch1_int;
dio_latch_time_ch1_o <= dio_latch_time_ch1_int and (not dio_latch_time_ch1_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch2_dly0 <= '0';
dio_latch_time_ch2_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch2_dly0 <= dio_latch_time_ch2_int;
dio_latch_time_ch2_o <= dio_latch_time_ch2_int and (not dio_latch_time_ch2_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch3_dly0 <= '0';
dio_latch_time_ch3_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch3_dly0 <= dio_latch_time_ch3_int;
dio_latch_time_ch3_o <= dio_latch_time_ch3_int and (not dio_latch_time_ch3_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch4_dly0 <= '0';
dio_latch_time_ch4_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch4_dly0 <= dio_latch_time_ch4_int;
dio_latch_time_ch4_o <= dio_latch_time_ch4_int and (not dio_latch_time_ch4_dly0);
end if;
end process;
-- trig_rdy field
-- pulse_gen_now_0
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_0_o <= '0';
dio_puls_inmed_pul_inm_0_sync0 <= '0';
dio_puls_inmed_pul_inm_0_sync1 <= '0';
dio_puls_inmed_pul_inm_0_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_0_sync0 <= dio_puls_inmed_pul_inm_0_int;
dio_puls_inmed_pul_inm_0_sync1 <= dio_puls_inmed_pul_inm_0_sync0;
dio_puls_inmed_pul_inm_0_sync2 <= dio_puls_inmed_pul_inm_0_sync1;
dio_puls_inmed_pul_inm_0_o <= dio_puls_inmed_pul_inm_0_sync2 and (not dio_puls_inmed_pul_inm_0_sync1);
end if;
end process;
-- pulse_gen_now_1
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_1_o <= '0';
dio_puls_inmed_pul_inm_1_sync0 <= '0';
dio_puls_inmed_pul_inm_1_sync1 <= '0';
dio_puls_inmed_pul_inm_1_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_1_sync0 <= dio_puls_inmed_pul_inm_1_int;
dio_puls_inmed_pul_inm_1_sync1 <= dio_puls_inmed_pul_inm_1_sync0;
dio_puls_inmed_pul_inm_1_sync2 <= dio_puls_inmed_pul_inm_1_sync1;
dio_puls_inmed_pul_inm_1_o <= dio_puls_inmed_pul_inm_1_sync2 and (not dio_puls_inmed_pul_inm_1_sync1);
end if;
end process;
-- pulse_gen_now_2
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_2_o <= '0';
dio_puls_inmed_pul_inm_2_sync0 <= '0';
dio_puls_inmed_pul_inm_2_sync1 <= '0';
dio_puls_inmed_pul_inm_2_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_2_sync0 <= dio_puls_inmed_pul_inm_2_int;
dio_puls_inmed_pul_inm_2_sync1 <= dio_puls_inmed_pul_inm_2_sync0;
dio_puls_inmed_pul_inm_2_sync2 <= dio_puls_inmed_pul_inm_2_sync1;
dio_puls_inmed_pul_inm_2_o <= dio_puls_inmed_pul_inm_2_sync2 and (not dio_puls_inmed_pul_inm_2_sync1);
end if;
end process;
-- pulse_gen_now_3
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_3_o <= '0';
dio_puls_inmed_pul_inm_3_sync0 <= '0';
dio_puls_inmed_pul_inm_3_sync1 <= '0';
dio_puls_inmed_pul_inm_3_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_3_sync0 <= dio_puls_inmed_pul_inm_3_int;
dio_puls_inmed_pul_inm_3_sync1 <= dio_puls_inmed_pul_inm_3_sync0;
dio_puls_inmed_pul_inm_3_sync2 <= dio_puls_inmed_pul_inm_3_sync1;
dio_puls_inmed_pul_inm_3_o <= dio_puls_inmed_pul_inm_3_sync2 and (not dio_puls_inmed_pul_inm_3_sync1);
end if;
end process;
-- pulse_gen_now_4
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_4_o <= '0';
dio_puls_inmed_pul_inm_4_sync0 <= '0';
dio_puls_inmed_pul_inm_4_sync1 <= '0';
dio_puls_inmed_pul_inm_4_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_4_sync0 <= dio_puls_inmed_pul_inm_4_int;
dio_puls_inmed_pul_inm_4_sync1 <= dio_puls_inmed_pul_inm_4_sync0;
dio_puls_inmed_pul_inm_4_sync2 <= dio_puls_inmed_pul_inm_4_sync1;
dio_puls_inmed_pul_inm_4_o <= dio_puls_inmed_pul_inm_4_sync2 and (not dio_puls_inmed_pul_inm_4_sync1);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 5,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 3,
g_irq04_mode => 3,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_nempty_0_i;
irq_inputs_vector_int(1) <= irq_nempty_1_i;
irq_inputs_vector_int(2) <= irq_nempty_2_i;
irq_inputs_vector_int(3) <= irq_nempty_3_i;
irq_inputs_vector_int(4) <= irq_nempty_4_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf0_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf0_rdreq_int_d0 <= dio_tsf0_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf1_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf1_rdreq_int_d0 <= dio_tsf1_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf2_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf2_rdreq_int_d0 <= dio_tsf2_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf3_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf3_rdreq_int_d0 <= dio_tsf3_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf4_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf4_rdreq_int_d0 <= dio_tsf4_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 2
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;