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FMC DIO 5ch TTL a
Commit 1f1c7a22 authored by Jorge Machado's avatar Jorge Machado
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Gateware WR-starting-kit review changes

parent b2976705
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hdl/modules/wr_dio/imm_pulse_train_gen.vhd
View file @ 1f1c7a22
......@@ -23,10 +23,10 @@ use IEEE.NUMERIC_STD.ALL;
--use UNISIM.VComponents.all;
entity imm_pulse_train_gen is
generic(
pulse_period_width : integer := 28
);
port(
generic(
pulse_period_width : integer := 28
);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_pulse_immed_stb_i : in std_logic;
......@@ -36,22 +36,24 @@ entity imm_pulse_train_gen is
end imm_pulse_train_gen;
architecture Behavioral of imm_pulse_train_gen is
signal nozeroperiod, nozeroperiod_aux : boolean;
signal dio_pulse_immed_stb_d0, dio_pulse_immed_stb_d1,
dio_pulse_immed_stb_d2, dio_pulse_immed_stb_d3 : std_logic;
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_period_width-1 downto 0);
signal nozeroperiod, nozeroperiod_aux : boolean;
signal pulse_period : std_logic_vector(pulse_period_width-1 downto 0);
signal dio_pulse_immed_stb_d0, dio_pulse_immed_stb_d1,
dio_pulse_immed_stb_d2, dio_pulse_immed_stb_d3 : std_logic;
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_period_width-1 downto 0);
-- Signals for states
type counter_state is (WAIT_ST, COUNTING, CAPTURE_PERIOD, TRIGGER);
signal state : counter_state;
signal repeat_pulse : std_logic;
-- Aux
-- Signals for states
type counter_state is (WAIT_ST, COUNTING, CAPTURE_PERIOD, TRIGGER);
signal state : counter_state;
signal repeat_pulse : std_logic;
-- Aux
constant zeros : std_logic_vector(pulse_period_width-1 downto 0) := (others => '0');
constant initial_pulse_delay_compensation : integer := 7;
......@@ -59,68 +61,70 @@ architecture Behavioral of imm_pulse_train_gen is
begin
synchronization : process(clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_pulse_immed_stb_d0 <= '0';
dio_pulse_immed_stb_d1 <= '0';
dio_pulse_immed_stb_d2 <= '0';
dio_pulse_immed_stb_d3 <= '0';
elsif rising_edge(clk_ref_i) then
dio_pulse_immed_stb_d0 <= dio_pulse_immed_stb_i;
dio_pulse_immed_stb_d1 <= dio_pulse_immed_stb_d0;
dio_pulse_immed_stb_d2 <= dio_pulse_immed_stb_d1;
dio_pulse_immed_stb_d3 <= dio_pulse_immed_stb_d2;
nozeroperiod_aux <= pulse_period_i /= zeros;
if ((dio_pulse_immed_stb_d2 = '1' and dio_pulse_immed_stb_d1 = '0') or (state = CAPTURE_PERIOD)) then
nozeroperiod <= nozeroperiod_aux;
end if;
end if;
end process;
state_process : process(clk_ref_i, rst_n_i)
begin
synchronization : process(clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_pulse_immed_stb_d0 <= '0';
dio_pulse_immed_stb_d1 <= '0';
dio_pulse_immed_stb_d2 <= '0';
dio_pulse_immed_stb_d3 <= '0';
elsif rising_edge(clk_ref_i) then
dio_pulse_immed_stb_d0 <= dio_pulse_immed_stb_i;
dio_pulse_immed_stb_d1 <= dio_pulse_immed_stb_d0;
dio_pulse_immed_stb_d2 <= dio_pulse_immed_stb_d1;
dio_pulse_immed_stb_d3 <= dio_pulse_immed_stb_d2;
--pulse_period <= pulse_period_i;
nozeroperiod_aux <= pulse_period_i /= zeros;
if ((dio_pulse_immed_stb_d2 = '1' and dio_pulse_immed_stb_d1 = '0') or (state = CAPTURE_PERIOD)) then
nozeroperiod <= nozeroperiod_aux;
pulse_period <= pulse_period_i;
end if;
end if;
end process;
state_process : process(clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
counter <= (others => '0');
state <= WAIT_ST;
repeat_pulse <= '0';
counter <= (others => '0');
state <= WAIT_ST;
repeat_pulse <= '0';
elsif rising_edge(clk_ref_i) then
case state is
when WAIT_ST =>
if dio_pulse_immed_stb_d3 = '1' and nozeroperiod then
state <= COUNTING;
--Store the period two cycle before than the immed_pulse_counter_process to not lost one cycle.
counter <= unsigned(pulse_period_i)-initial_pulse_delay_compensation;
elsif repeat_pulse = '1' and nozeroperiod then
state <= COUNTING;
--Store the period four cycles before
counter <= unsigned(pulse_period_i)-repeat_pulse_delay_compensation;
else
state <= WAIT_ST;
end if;
when COUNTING =>
if (counter = 0) then
state <= CAPTURE_PERIOD;
else
state <= COUNTING;
counter <= counter-1;
end if;
when CAPTURE_PERIOD =>
state <= TRIGGER;
when TRIGGER =>
state <= WAIT_ST;
if(nozeroperiod) then
repeat_pulse <= '1';
else
repeat_pulse <= '0';
end if;
when others =>
state <= WAIT_ST;
end case;
end if;
end process;
output_process : process(counter, state)
when WAIT_ST =>
if dio_pulse_immed_stb_d3 = '1' and nozeroperiod then
state <= COUNTING;
--Store the period two cycle before than the immed_pulse_counter_process to not lost one cycle.
counter <= unsigned(pulse_period)-initial_pulse_delay_compensation;
elsif repeat_pulse = '1' and nozeroperiod then
state <= COUNTING;
--Store the period four cycles before
counter <= unsigned(pulse_period)-repeat_pulse_delay_compensation;
else
state <= WAIT_ST;
end if;
when COUNTING =>
if (counter = 0) then
state <= CAPTURE_PERIOD;
else
state <= COUNTING;
counter <= counter-1;
end if;
when CAPTURE_PERIOD =>
state <= TRIGGER;
when TRIGGER =>
state <= WAIT_ST;
if(nozeroperiod) then
repeat_pulse <= '1';
else
repeat_pulse <= '0';
end if;
when others =>
state <= WAIT_ST;
end case;
end if;
end process;
output_process : process(rst_n_i, state)
begin
if (rst_n_i = '0') then
pulse_output_o <= '0';
......@@ -129,9 +133,9 @@ begin
when WAIT_ST =>
pulse_output_o <= '0';
when COUNTING =>
pulse_output_o <= '0';
when TRIGGER =>
pulse_output_o <= '1';
pulse_output_o <= '0';
when TRIGGER =>
pulse_output_o <= '1';
when others =>
pulse_output_o <= '0';
end case;
......
hdl/modules/wr_dio/immed_pulse_counter.vhd
View file @ 1f1c7a22
......@@ -66,6 +66,8 @@ architecture rtl of immed_pulse_counter is
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others => '0');
signal pulse_length : std_logic_vector(pulse_length_width-1 downto 0);
begin -- architecture rtl
synchronization : process(clk_i, rst_n_i)
......@@ -81,8 +83,10 @@ begin -- architecture rtl
pulse_start_d2 <= pulse_start_d1;
pulse_start_d3 <= pulse_start_d2;
nozerolength_aux <= pulse_length_i /= zeros;
--pulse_length <= pulse_length_i;
if (pulse_start_d2 = '1' and pulse_start_d1 = '0') then
nozerolength <= nozerolength_aux;
nozerolength <= nozerolength_aux;
pulse_length <= pulse_length_i;
end if;
end if;
end process;
......@@ -97,7 +101,7 @@ begin -- architecture rtl
when WAIT_ST =>
if pulse_start_d3 = '1' and nozerolength then
state <= COUNTING;
counter <= unsigned(pulse_length_i)-1;
counter <= unsigned(pulse_length)-1;
else
state <= WAIT_ST;
end if;
......@@ -114,7 +118,7 @@ begin -- architecture rtl
end if;
end process;
output_process : process(counter, state)
output_process : process(rst_n_i, state)
begin
if (rst_n_i = '0') then
pulse_output_o <= '0';
......
hdl/modules/wr_dio/pulse_gen_pl.vhd
View file @ 1f1c7a22
......@@ -220,7 +220,7 @@ begin -- architecture rtl
train_counter <= unsigned(pulse_period_ref); --Store the value of the period
elsif counter /= 0 then --The period counter is reduced at the same time than the pulse counter
counter <= counter-1;
if(nozeroperiod) then
if(train_counter /= 0) then
train_counter <= train_counter-1;
end if;
-- elsif(train_counter = 10) then --Load new values for then next cycle
......
hdl/modules/wr_dio/wr_dio.wb
View file @ 1f1c7a22
......@@ -48,7 +48,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf0";
name = "Timestamp FIFO 0";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - seconds time\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -114,7 +114,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf1";
name = "Timestamp FIFO 1";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -180,7 +180,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf2";
name = "Timestamp FIFO 2";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -245,7 +245,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf3";
name = "Timestamp FIFO 3";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -310,7 +310,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf4";
name = "Timestamp FIFO 4";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -375,7 +375,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf5";
name = "Timestamp FIFO 5";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......
hdl/modules/wr_dio/xwr_dio.vhd
View file @ 1f1c7a22
......@@ -154,7 +154,7 @@ architecture rtl of xwr_dio is
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0);
pulse_period_i : in std_logic_vector(27 downto 0)
pulse_period_i : in std_logic_vector(27 downto 0)
);
end component;
......@@ -212,9 +212,9 @@ architecture rtl of xwr_dio is
end component;
component imm_pulse_train_gen
generic(
pulse_period_width : integer := 28
);
generic(
pulse_period_width : integer := 28
);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
......@@ -225,210 +225,210 @@ architecture rtl of xwr_dio is
end component;
component wr_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- Port for std_logic_vector field: 'Version identifier' in reg: 'Version register'
dio_ver_id_o : out std_logic_vector(31 downto 0);
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf0_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf0_leap_second_valid_i : in std_logic;
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf1_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf1_leap_second_valid_i : in std_logic;
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf2_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf2_leap_second_valid_i : in std_logic;
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf3_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf3_leap_second_valid_i : in std_logic;
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf4_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf4_leap_second_valid_i : in std_logic;
irq_nempty_4_i : in std_logic;
-- FIFO write request
dio_tsf5_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf5_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf5_wr_empty_o : out std_logic;
dio_tsf5_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf5_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf5_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf5_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf5_leap_second_valid_i : in std_logic;
irq_nempty_5_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trig5_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trigh5_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 5 cycles to trigger a pulse generation'
dio_cyc5_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'channel0' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
dio_iomode_ch0_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch1_o : out std_logic_vector(3 downto 0);
dio_iomode_ch1_i : in std_logic_vector(3 downto 0);
dio_iomode_ch1_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch2_o : out std_logic_vector(3 downto 0);
dio_iomode_ch2_i : in std_logic_vector(3 downto 0);
dio_iomode_ch2_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch3_o : out std_logic_vector(3 downto 0);
dio_iomode_ch3_i : in std_logic_vector(3 downto 0);
dio_iomode_ch3_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel5' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch5_o : out std_logic_vector(3 downto 0);
dio_iomode_ch5_i : in std_logic_vector(3 downto 0);
dio_iomode_ch5_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch5_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(5 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
irq_trigger_ready_5_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse period'
dio_prog0_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse period'
dio_prog1_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse period'
dio_prog2_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse period'
dio_prog3_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse period'
dio_prog4_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse length'
dio_prog5_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse period'
dio_prog5_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_5' in reg: 'Pulse generate immediately'
dio_pulse_imm_5_o : out std_logic
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- Port for std_logic_vector field: 'Version identifier' in reg: 'Version register'
dio_ver_id_o : out std_logic_vector(31 downto 0);
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf0_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf0_leap_second_valid_i : in std_logic;
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf1_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf1_leap_second_valid_i : in std_logic;
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf2_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf2_leap_second_valid_i : in std_logic;
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf3_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf3_leap_second_valid_i : in std_logic;
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf4_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf4_leap_second_valid_i : in std_logic;
irq_nempty_4_i : in std_logic;
-- FIFO write request
dio_tsf5_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf5_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf5_wr_empty_o : out std_logic;
dio_tsf5_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf5_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf5_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf5_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf5_leap_second_valid_i : in std_logic;
irq_nempty_5_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trig5_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trigh5_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 5 cycles to trigger a pulse generation'
dio_cyc5_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'channel0' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
dio_iomode_ch0_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch1_o : out std_logic_vector(3 downto 0);
dio_iomode_ch1_i : in std_logic_vector(3 downto 0);
dio_iomode_ch1_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch2_o : out std_logic_vector(3 downto 0);
dio_iomode_ch2_i : in std_logic_vector(3 downto 0);
dio_iomode_ch2_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch3_o : out std_logic_vector(3 downto 0);
dio_iomode_ch3_i : in std_logic_vector(3 downto 0);
dio_iomode_ch3_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel5' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch5_o : out std_logic_vector(3 downto 0);
dio_iomode_ch5_i : in std_logic_vector(3 downto 0);
dio_iomode_ch5_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch5_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(5 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
irq_trigger_ready_5_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse period'
dio_prog0_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse period'
dio_prog1_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse period'
dio_prog2_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse period'
dio_prog3_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse period'
dio_prog4_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse length'
dio_prog5_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse period'
dio_prog5_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_5' in reg: 'Pulse generate immediately'
dio_pulse_imm_5_o : out std_logic
);
end component;
......@@ -522,7 +522,13 @@ architecture rtl of xwr_dio is
signal dio_led_bot_o_ch : std_logic_vector(4 downto 0);
signal dio_prog_interrupt : std_logic;
signal dio_prog_interrupt : std_logic;
signal dio_prog_interrupt_reg_d0 : std_logic;
signal dio_prog_interrupt_reg_d1 : std_logic;
-- Register the final output signal to force the IOB and avoid any glitches.
signal dio_out_reg : std_logic_vector(5 downto 0);
signal dio_in_reg : std_logic_vector(5 downto 0);
-------------------------------------------------------------------------------
-- rtl
......@@ -563,8 +569,7 @@ begin
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i),
pulse_length_i => pulse_length(i),
pulse_period_i => pulse_period(i)
);
pulse_period_i => pulse_period(i));
U_PULSE_STAMPER : pulse_stamper
......@@ -586,73 +591,70 @@ begin
tag_tai_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_o => tag_valid_p1(i));
end generate gen_pulse_modules;
U_pulse_gen : pulse_gen_pl
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_pulse_prog(5),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_seconds,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(5),
trig_utc_i => trig_seconds(5),
trig_cycles_i => trig_cycles(5),
trig_valid_p1_i => trig_valid_p1(5),
pulse_length_i => pulse_length(5),
pulse_period_i => pulse_period(5)
);
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
U_PULSE_STAMPER : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_pulse_prog(5),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_seconds,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(5),
trig_utc_i => trig_seconds(5),
trig_cycles_i => trig_cycles(5),
trig_valid_p1_i => trig_valid_p1(5),
pulse_length_i => pulse_length(5),
pulse_period_i => pulse_period(5));
U_PULSE_STAMPER : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => dio_prog_interrupt,
pulse_a_i => dio_prog_interrupt_reg_d1,
-- DEBUG
-- tm_time_valid_i => '1',
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
-- DEBUG
-- tm_time_valid_i => '1',
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tag_tai_o => tag_seconds(5),
tag_cycles_o => tag_cycles(5),
tag_valid_o => tag_valid_p1(5));
tag_tai_o => tag_seconds(5),
tag_cycles_o => tag_cycles(5),
tag_valid_o => tag_valid_p1(5));
------------------------------------------------------------------------------
-- PULSE TRAIN GENERATOR
------------------------------------------------------------------------------
gen_pulse_train_modules : for i in 0 to 5 generate
U_imm_pulse_train_gen : imm_pulse_train_gen
generic map(
pulse_period_width => 28
)
port map(
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_pulse_immed_stb_i => dio_pulse_immed_stb(i),
pulse_period_i => pulse_period(i),
pulse_output_o => dio_pulse_immed_periodic(i)
);
gen_pulse_train_modules : for i in 0 to 5 generate
U_imm_pulse_train_gen : imm_pulse_train_gen
generic map(
pulse_period_width => 28
)
port map(
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_pulse_immed_stb_i => dio_pulse_immed_stb(i),
pulse_period_i => pulse_period(i),
pulse_output_o => dio_pulse_immed_periodic(i)
);
end generate gen_pulse_train_modules;
end generate gen_pulse_train_modules;
------------------------------------------------------------------------------
-- WB ONEWIRE MASTER
......@@ -791,11 +793,11 @@ begin
end generate immediate_output_with_pulse_length;
gen_pio_assignment : for i in 0 to 4 generate
gpio_in(c_IOMODE_NB*i) <= dio_in_i(i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
gpio_in(c_IOMODE_NB*i) <= dio_in_reg(i);
dio_pulse(i) <= dio_pulse_immed(i) or dio_pulse_prog(i);
dio_oe_n_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+2);
dio_term_en_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+3);
dio_out_o(i) <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "00" else dio_pulse(i);
dio_out_reg(i) <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "00" else dio_pulse(i);
--with dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i)
--select dio_out_o(i) <=
......@@ -806,6 +808,26 @@ begin
end generate gen_pio_assignment;
--Register input and output to force the IOB and avoid any glitches
input_output_register : for i in 0 to 5 generate
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
dio_out_o(i) <= dio_out_reg(i);
dio_in_reg(i) <= dio_in_i(i);
end if;
end process;
end generate input_output_register;
--Register irq to compensate the delay of the physical outputs
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
dio_prog_interrupt_reg_d0 <= dio_prog_interrupt;
dio_prog_interrupt_reg_d1 <= dio_prog_interrupt_reg_d0;
end if;
end process;
--New channel programmed pulse has been connected directly to the input to generate the timestamp of each interrupt
dio_prog_interrupt <= dio_pulse_prog(5) or dio_pulse_immed(5) when dio_iomode_reg(c_IOMODE_NB*5) = '1' else '0';
......@@ -876,16 +898,16 @@ begin
-- Crossbar could not propagate interrupt lines of several slaves => signal bypass
wb_int_o => wb_dio_irq,
clk_asyn_i => clk_ref_i,
dio_ver_id_o => open,
dio_ver_id_o => open,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
dio_tsf0_wr_full_o => dio_tsf_wr_full(0),
dio_tsf0_wr_empty_o => dio_tsf_wr_empty(0),
dio_tsf0_tag_seconds_i => dio_tsf_tag_seconds(0)(31 downto 0),
dio_tsf0_tag_secondsh_i => dio_tsf_tag_seconds(0)(39 downto 32),
dio_tsf0_tag_cycles_i => dio_tsf_tag_cycles(0),
dio_tsf0_leap_second_value_i => dio_tsf_leap_second(0),
dio_tsf0_leap_second_valid_i => dio_tsf_leap_second_valid(0),
dio_tsf0_leap_second_value_i => dio_tsf_leap_second(0),
dio_tsf0_leap_second_valid_i => dio_tsf_leap_second_valid(0),
irq_nempty_0_i => irq_nempty(0),
dio_tsf1_wr_req_i => dio_tsf_wr_req(1),
......@@ -894,8 +916,8 @@ begin
dio_tsf1_tag_seconds_i => dio_tsf_tag_seconds(1)(31 downto 0),
dio_tsf1_tag_secondsh_i => dio_tsf_tag_seconds(1)(39 downto 32),
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
dio_tsf1_leap_second_value_i => dio_tsf_leap_second(1),
dio_tsf1_leap_second_valid_i => dio_tsf_leap_second_valid(1),
dio_tsf1_leap_second_value_i => dio_tsf_leap_second(1),
dio_tsf1_leap_second_valid_i => dio_tsf_leap_second_valid(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
......@@ -904,8 +926,8 @@ begin
dio_tsf2_tag_seconds_i => dio_tsf_tag_seconds(2)(31 downto 0),
dio_tsf2_tag_secondsh_i => dio_tsf_tag_seconds(2)(39 downto 32),
dio_tsf2_tag_cycles_i => dio_tsf_tag_cycles(2),
dio_tsf2_leap_second_value_i => dio_tsf_leap_second(2),
dio_tsf2_leap_second_valid_i => dio_tsf_leap_second_valid(2),
dio_tsf2_leap_second_value_i => dio_tsf_leap_second(2),
dio_tsf2_leap_second_valid_i => dio_tsf_leap_second_valid(2),
irq_nempty_2_i => irq_nempty(2),
dio_tsf3_wr_req_i => dio_tsf_wr_req(3),
......@@ -914,8 +936,8 @@ begin
dio_tsf3_tag_seconds_i => dio_tsf_tag_seconds(3)(31 downto 0),
dio_tsf3_tag_secondsh_i => dio_tsf_tag_seconds(3)(39 downto 32),
dio_tsf3_tag_cycles_i => dio_tsf_tag_cycles(3),
dio_tsf3_leap_second_value_i => dio_tsf_leap_second(3),
dio_tsf3_leap_second_valid_i => dio_tsf_leap_second_valid(3),
dio_tsf3_leap_second_value_i => dio_tsf_leap_second(3),
dio_tsf3_leap_second_valid_i => dio_tsf_leap_second_valid(3),
irq_nempty_3_i => irq_nempty(3),
dio_tsf4_wr_req_i => dio_tsf_wr_req(4),
......@@ -924,18 +946,18 @@ begin
dio_tsf4_tag_seconds_i => dio_tsf_tag_seconds(4)(31 downto 0),
dio_tsf4_tag_secondsh_i => dio_tsf_tag_seconds(4)(39 downto 32),
dio_tsf4_tag_cycles_i => dio_tsf_tag_cycles(4),
dio_tsf4_leap_second_value_i => dio_tsf_leap_second(4),
dio_tsf4_leap_second_valid_i => dio_tsf_leap_second_valid(4),
dio_tsf4_leap_second_value_i => dio_tsf_leap_second(4),
dio_tsf4_leap_second_valid_i => dio_tsf_leap_second_valid(4),
irq_nempty_4_i => irq_nempty(4),
dio_tsf5_wr_req_i => dio_tsf_wr_req(5),
dio_tsf5_wr_req_i => dio_tsf_wr_req(5),
dio_tsf5_wr_full_o => dio_tsf_wr_full(5),
dio_tsf5_wr_empty_o => dio_tsf_wr_empty(5),
dio_tsf5_tag_seconds_i => dio_tsf_tag_seconds(5)(31 downto 0),
dio_tsf5_tag_secondsh_i => dio_tsf_tag_seconds(5)(39 downto 32),
dio_tsf5_tag_cycles_i => dio_tsf_tag_cycles(5),
dio_tsf5_leap_second_value_i => dio_tsf_leap_second(5),
dio_tsf5_leap_second_valid_i => dio_tsf_leap_second_valid(5),
dio_tsf5_leap_second_value_i => dio_tsf_leap_second(5),
dio_tsf5_leap_second_valid_i => dio_tsf_leap_second_valid(5),
irq_nempty_5_i => irq_nempty(5),
dio_trig0_seconds_o => trig_seconds(0)(31 downto 0),
......@@ -957,8 +979,8 @@ begin
dio_trig4_seconds_o => trig_seconds(4)(31 downto 0),
dio_trigh4_seconds_o => trig_seconds(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4),
dio_trig5_seconds_o => trig_seconds(5)(31 downto 0),
dio_trig5_seconds_o => trig_seconds(5)(31 downto 0),
dio_trigh5_seconds_o => trig_seconds(5)(39 downto 32),
dio_cyc5_cyc_o => trig_cycles(5),
......@@ -967,28 +989,28 @@ begin
dio_iomode_ch2_i => dio_iomode_reg(11 downto 8),
dio_iomode_ch3_i => dio_iomode_reg(15 downto 12),
dio_iomode_ch4_i => dio_iomode_reg(19 downto 16),
dio_iomode_ch5_i => dio_iomode_reg(23 downto 20),
dio_iomode_ch5_i => dio_iomode_reg(23 downto 20),
dio_iomode_ch0_o => dio_iomode_o(3 downto 0),
dio_iomode_ch1_o => dio_iomode_o(7 downto 4),
dio_iomode_ch2_o => dio_iomode_o(11 downto 8),
dio_iomode_ch3_o => dio_iomode_o(15 downto 12),
dio_iomode_ch4_o => dio_iomode_o(19 downto 16),
dio_iomode_ch5_o => dio_iomode_o(23 downto 20),
dio_iomode_ch5_o => dio_iomode_o(23 downto 20),
dio_iomode_ch0_load_o => dio_iomode_load_o(0),
dio_iomode_ch1_load_o => dio_iomode_load_o(1),
dio_iomode_ch2_load_o => dio_iomode_load_o(2),
dio_iomode_ch3_load_o => dio_iomode_load_o(3),
dio_iomode_ch4_load_o => dio_iomode_load_o(4),
dio_iomode_ch5_load_o => dio_iomode_load_o(5),
dio_iomode_ch5_load_o => dio_iomode_load_o(5),
dio_latch_time_ch0_o => trig_valid_p1(0),
dio_latch_time_ch1_o => trig_valid_p1(1),
dio_latch_time_ch2_o => trig_valid_p1(2),
dio_latch_time_ch3_o => trig_valid_p1(3),
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_latch_time_ch5_o => trig_valid_p1(5),
dio_latch_time_ch5_o => trig_valid_p1(5),
dio_trig_rdy_i => trig_ready,
......@@ -997,29 +1019,28 @@ begin
irq_trigger_ready_2_i => trig_ready(2),
irq_trigger_ready_3_i => trig_ready(3),
irq_trigger_ready_4_i => trig_ready(4),
irq_trigger_ready_5_i => trig_ready(5),
irq_trigger_ready_5_i => trig_ready(5),
dio_prog0_pulse_length_o => pulse_length(0),
dio_prog1_pulse_length_o => pulse_length(1),
dio_prog2_pulse_length_o => pulse_length(2),
dio_prog3_pulse_length_o => pulse_length(3),
dio_prog4_pulse_length_o => pulse_length(4),
dio_prog5_pulse_length_o => pulse_length(5),
dio_prog0_pulse_per_o => pulse_period(0),
dio_prog1_pulse_per_o => pulse_period(1),
dio_prog2_pulse_per_o => pulse_period(2),
dio_prog3_pulse_per_o => pulse_period(3),
dio_prog4_pulse_per_o => pulse_period(4),
dio_prog5_pulse_per_o => pulse_period(5),
dio_prog5_pulse_length_o => pulse_length(5),
dio_prog0_pulse_per_o => pulse_period(0),
dio_prog1_pulse_per_o => pulse_period(1),
dio_prog2_pulse_per_o => pulse_period(2),
dio_prog3_pulse_per_o => pulse_period(3),
dio_prog4_pulse_per_o => pulse_period(4),
dio_prog5_pulse_per_o => pulse_period(5),
dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_4_o => dio_pulse_immed_stb(4),
dio_pulse_imm_5_o => dio_pulse_immed_stb(5)
);
dio_pulse_imm_5_o => dio_pulse_immed_stb(5));
-- seconds timestamped FIFO-no-empty interrupts
irq_nempty(0) <= not dio_tsf_wr_empty(0);
......
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