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FMC DIO 5ch TTL a
Commit 1f1c7a22 authored by Jorge Machado's avatar Jorge Machado
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Gateware WR-starting-kit review changes

parent b2976705
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hdl/modules/wr_dio/imm_pulse_train_gen.vhd
View file @ 1f1c7a22
......@@ -39,6 +39,8 @@ architecture Behavioral of imm_pulse_train_gen is
signal nozeroperiod, nozeroperiod_aux : boolean;
signal pulse_period : std_logic_vector(pulse_period_width-1 downto 0);
signal dio_pulse_immed_stb_d0, dio_pulse_immed_stb_d1,
dio_pulse_immed_stb_d2, dio_pulse_immed_stb_d3 : std_logic;
......@@ -71,9 +73,11 @@ begin
dio_pulse_immed_stb_d1 <= dio_pulse_immed_stb_d0;
dio_pulse_immed_stb_d2 <= dio_pulse_immed_stb_d1;
dio_pulse_immed_stb_d3 <= dio_pulse_immed_stb_d2;
--pulse_period <= pulse_period_i;
nozeroperiod_aux <= pulse_period_i /= zeros;
if ((dio_pulse_immed_stb_d2 = '1' and dio_pulse_immed_stb_d1 = '0') or (state = CAPTURE_PERIOD)) then
nozeroperiod <= nozeroperiod_aux;
pulse_period <= pulse_period_i;
end if;
end if;
end process;
......@@ -90,11 +94,11 @@ begin
if dio_pulse_immed_stb_d3 = '1' and nozeroperiod then
state <= COUNTING;
--Store the period two cycle before than the immed_pulse_counter_process to not lost one cycle.
counter <= unsigned(pulse_period_i)-initial_pulse_delay_compensation;
counter <= unsigned(pulse_period)-initial_pulse_delay_compensation;
elsif repeat_pulse = '1' and nozeroperiod then
state <= COUNTING;
--Store the period four cycles before
counter <= unsigned(pulse_period_i)-repeat_pulse_delay_compensation;
counter <= unsigned(pulse_period)-repeat_pulse_delay_compensation;
else
state <= WAIT_ST;
end if;
......@@ -120,7 +124,7 @@ begin
end if;
end process;
output_process : process(counter, state)
output_process : process(rst_n_i, state)
begin
if (rst_n_i = '0') then
pulse_output_o <= '0';
......
hdl/modules/wr_dio/immed_pulse_counter.vhd
View file @ 1f1c7a22
......@@ -66,6 +66,8 @@ architecture rtl of immed_pulse_counter is
-- Aux
constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others => '0');
signal pulse_length : std_logic_vector(pulse_length_width-1 downto 0);
begin -- architecture rtl
synchronization : process(clk_i, rst_n_i)
......@@ -81,8 +83,10 @@ begin -- architecture rtl
pulse_start_d2 <= pulse_start_d1;
pulse_start_d3 <= pulse_start_d2;
nozerolength_aux <= pulse_length_i /= zeros;
--pulse_length <= pulse_length_i;
if (pulse_start_d2 = '1' and pulse_start_d1 = '0') then
nozerolength <= nozerolength_aux;
pulse_length <= pulse_length_i;
end if;
end if;
end process;
......@@ -97,7 +101,7 @@ begin -- architecture rtl
when WAIT_ST =>
if pulse_start_d3 = '1' and nozerolength then
state <= COUNTING;
counter <= unsigned(pulse_length_i)-1;
counter <= unsigned(pulse_length)-1;
else
state <= WAIT_ST;
end if;
......@@ -114,7 +118,7 @@ begin -- architecture rtl
end if;
end process;
output_process : process(counter, state)
output_process : process(rst_n_i, state)
begin
if (rst_n_i = '0') then
pulse_output_o <= '0';
......
hdl/modules/wr_dio/pulse_gen_pl.vhd
View file @ 1f1c7a22
......@@ -220,7 +220,7 @@ begin -- architecture rtl
train_counter <= unsigned(pulse_period_ref); --Store the value of the period
elsif counter /= 0 then --The period counter is reduced at the same time than the pulse counter
counter <= counter-1;
if(nozeroperiod) then
if(train_counter /= 0) then
train_counter <= train_counter-1;
end if;
-- elsif(train_counter = 10) then --Load new values for then next cycle
......
hdl/modules/wr_dio/wr_dio.wb
View file @ 1f1c7a22
......@@ -48,7 +48,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf0";
name = "Timestamp FIFO 0";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - seconds time\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -114,7 +114,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf1";
name = "Timestamp FIFO 1";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -180,7 +180,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf2";
name = "Timestamp FIFO 2";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -245,7 +245,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf3";
name = "Timestamp FIFO 3";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -310,7 +310,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf4";
name = "Timestamp FIFO 4";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......@@ -375,7 +375,7 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "tsf5";
name = "Timestamp FIFO 5";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting from the following values:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
......
hdl/modules/wr_dio/xwr_dio.vhd
View file @ 1f1c7a22
......@@ -523,6 +523,12 @@ architecture rtl of xwr_dio is
signal dio_prog_interrupt : std_logic;
signal dio_prog_interrupt_reg_d0 : std_logic;
signal dio_prog_interrupt_reg_d1 : std_logic;
-- Register the final output signal to force the IOB and avoid any glitches.
signal dio_out_reg : std_logic_vector(5 downto 0);
signal dio_in_reg : std_logic_vector(5 downto 0);
-------------------------------------------------------------------------------
-- rtl
......@@ -563,8 +569,7 @@ begin
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i),
pulse_length_i => pulse_length(i),
pulse_period_i => pulse_period(i)
);
pulse_period_i => pulse_period(i));
U_PULSE_STAMPER : pulse_stamper
......@@ -586,7 +591,6 @@ begin
tag_tai_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_o => tag_valid_p1(i));
end generate gen_pulse_modules;
U_pulse_gen : pulse_gen_pl
......@@ -597,9 +601,9 @@ begin
pulse_o => dio_pulse_prog(5),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_seconds,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_seconds,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
......@@ -610,9 +614,7 @@ begin
trig_cycles_i => trig_cycles(5),
trig_valid_p1_i => trig_valid_p1(5),
pulse_length_i => pulse_length(5),
pulse_period_i => pulse_period(5)
);
pulse_period_i => pulse_period(5));
U_PULSE_STAMPER : pulse_stamper
port map(
......@@ -620,12 +622,12 @@ begin
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => dio_prog_interrupt,
pulse_a_i => dio_prog_interrupt_reg_d1,
-- DEBUG
-- tm_time_valid_i => '1',
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
-- tm_time_valid_i => '1',
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
......@@ -791,11 +793,11 @@ begin
end generate immediate_output_with_pulse_length;
gen_pio_assignment : for i in 0 to 4 generate
gpio_in(c_IOMODE_NB*i) <= dio_in_i(i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
gpio_in(c_IOMODE_NB*i) <= dio_in_reg(i);
dio_pulse(i) <= dio_pulse_immed(i) or dio_pulse_prog(i);
dio_oe_n_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+2);
dio_term_en_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+3);
dio_out_o(i) <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "00" else dio_pulse(i);
dio_out_reg(i) <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "00" else dio_pulse(i);
--with dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i)
--select dio_out_o(i) <=
......@@ -806,6 +808,26 @@ begin
end generate gen_pio_assignment;
--Register input and output to force the IOB and avoid any glitches
input_output_register : for i in 0 to 5 generate
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
dio_out_o(i) <= dio_out_reg(i);
dio_in_reg(i) <= dio_in_i(i);
end if;
end process;
end generate input_output_register;
--Register irq to compensate the delay of the physical outputs
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
dio_prog_interrupt_reg_d0 <= dio_prog_interrupt;
dio_prog_interrupt_reg_d1 <= dio_prog_interrupt_reg_d0;
end if;
end process;
--New channel programmed pulse has been connected directly to the input to generate the timestamp of each interrupt
dio_prog_interrupt <= dio_pulse_prog(5) or dio_pulse_immed(5) when dio_iomode_reg(c_IOMODE_NB*5) = '1' else '0';
......@@ -1018,8 +1040,7 @@ begin
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_4_o => dio_pulse_immed_stb(4),
dio_pulse_imm_5_o => dio_pulse_immed_stb(5)
);
dio_pulse_imm_5_o => dio_pulse_immed_stb(5));
-- seconds timestamped FIFO-no-empty interrupts
irq_nempty(0) <= not dio_tsf_wr_empty(0);
......
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