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FMC DIO 5ch TTL a
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FMC DIO 5ch TTL a
Commits
37e705b5
Commit
37e705b5
authored
May 14, 2020
by
Jorge Machado
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Update WB and package files
parent
31e53528
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6 changed files
with
2802 additions
and
1840 deletions
+2802
-1840
wr_dio.wb
hdl/modules/wr_dio/wr_dio.wb
+499
-150
wr_dio_pkg.vhd
hdl/modules/wr_dio/wr_dio_pkg.vhd
+2
-2
wr_dio_wb.vhd
hdl/modules/wr_dio/wr_dio_wb.vhd
+2073
-1518
xwr_dio.vhd
hdl/modules/wr_dio/xwr_dio.vhd
+213
-161
dio_common_top.vhd
hdl/top/dio-common/dio_common_top.vhd
+14
-8
dio_common_top_pkg.vhd
hdl/top/dio-common/dio_common_top_pkg.vhd
+1
-1
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hdl/modules/wr_dio/wr_dio.wb
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37e705b5
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hdl/modules/wr_dio/wr_dio_pkg.vhd
View file @
37e705b5
...
...
@@ -70,10 +70,10 @@ package wr_dio_pkg is
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000000
0
ff"
,
addr_last
=>
x"0000000000000
3
ff"
,
product
=>
(
vendor_id
=>
x"00000000000075CB"
,
-- SEVEN SOLUTIONS
device_id
=>
x"0000000
1
"
,
device_id
=>
x"0000000
3
"
,
version
=>
x"00000002"
,
date
=>
x"20120709"
,
name
=>
"WR-DIO-Registers "
)));
...
...
hdl/modules/wr_dio/wr_dio_wb.vhd
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37e705b5
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hdl/modules/wr_dio/xwr_dio.vhd
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37e705b5
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hdl/top/dio-common/dio_common_top.vhd
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37e705b5
...
...
@@ -240,10 +240,10 @@ architecture top of dio_common_top is
dio_clk_i
:
in
std_logic
;
dio_pps_i
:
in
std_logic
;
dio_in_i
:
in
std_logic_vector
(
4
downto
0
);
dio_out_o
:
out
std_logic_vector
(
4
downto
0
);
dio_oe_n_o
:
out
std_logic_vector
(
4
downto
0
);
dio_term_en_o
:
out
std_logic_vector
(
4
downto
0
);
dio_in_i
:
in
std_logic_vector
(
5
downto
0
);
dio_out_o
:
out
std_logic_vector
(
5
downto
0
);
dio_oe_n_o
:
out
std_logic_vector
(
5
downto
0
);
dio_term_en_o
:
out
std_logic_vector
(
5
downto
0
);
dio_onewire_b
:
inout
std_logic
;
dio_sdn_n_o
:
out
std_logic
;
dio_sdn_ck_n_o
:
out
std_logic
;
...
...
@@ -325,8 +325,8 @@ architecture top of dio_common_top is
signal
svec_led
:
std_logic_vector
(
15
downto
0
);
-- DIO Mezzanine
signal
dio_in
:
std_logic_vector
(
4
downto
0
);
signal
dio_out
:
std_logic_vector
(
4
downto
0
);
signal
dio_in
:
std_logic_vector
(
5
downto
0
);
signal
dio_out
:
std_logic_vector
(
5
downto
0
);
-- Timecode output
signal
tm_time_valid
:
std_logic
;
...
...
@@ -349,6 +349,9 @@ architecture top of dio_common_top is
-- VIC-only signals
signal
vic_only_irqs
:
std_logic_vector
(
3
downto
0
);
signal
dio_oe_n_o_internal
:
std_logic_vector
(
5
downto
0
);
signal
dio_term_en_o_internal
:
std_logic_vector
(
5
downto
0
);
begin
-- architecture top
...
...
@@ -663,8 +666,8 @@ begin -- architecture top
dio_pps_i
=>
wrc_pps_out
,
dio_in_i
=>
dio_in
,
dio_out_o
=>
dio_out
,
dio_oe_n_o
=>
dio_oe_n_o
,
dio_term_en_o
=>
dio_term_en_o
,
dio_oe_n_o
=>
dio_oe_n_o
_internal
,
dio_term_en_o
=>
dio_term_en_o
_internal
,
dio_onewire_b
=>
dio_onewire_b
,
dio_sdn_n_o
=>
dio_sdn_n_o
,
dio_sdn_ck_n_o
=>
dio_sdn_ck_n_o
,
...
...
@@ -679,6 +682,9 @@ begin -- architecture top
dio_int
=>
dio_int
);
dio_oe_n_o
<=
dio_oe_n_o_internal
(
4
downto
0
);
dio_term_en_o
<=
dio_term_en_o_internal
(
4
downto
0
);
vic_vec_int
(
0
)
<=
dio_int
;
NIC_GEN
:
if
g_dio_mode
=
DIO_NIC
generate
...
...
hdl/top/dio-common/dio_common_top_pkg.vhd
View file @
37e705b5
...
...
@@ -238,7 +238,7 @@ package dio_common_top_pkg is
constant
c_nic_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0001ffff"
,
x"00011000"
);
constant
c_wr_dio_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_product_manual_sdb
(
x"00000fff"
,
x"00000
4
00"
,
c_xwr_dio_sdb
);
f_xwb_bridge_product_manual_sdb
(
x"00000fff"
,
x"00000
8
00"
,
c_xwr_dio_sdb
);
-- Primary wishbone crossbar layout (NIC)
constant
c_NIC_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
...
...
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