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FMC DIO 5ch TTL a
Commits
3b614a4b
Commit
3b614a4b
authored
May 27, 2019
by
Miguel Jimenez Lopez
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hdl: Update DIO designs to use NIC-related cores outside from the xwr_board_common block.
parent
97c0d08f
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3 changed files
with
138 additions
and
48 deletions
+138
-48
wr-cores
hdl/ip_cores/wr-cores
+1
-1
dio_common_top.vhd
hdl/top/dio-common/dio_common_top.vhd
+82
-44
dio_common_top_pkg.vhd
hdl/top/dio-common/dio_common_top_pkg.vhd
+55
-3
No files found.
wr-cores
@
6f9c1177
Subproject commit
e2f7cce74217c61f4e02f0b80b55deeb92d8b6f4
Subproject commit
6f9c1177a98f50fed036c6650305b936597895a9
hdl/top/dio-common/dio_common_top.vhd
View file @
3b614a4b
...
...
@@ -11,8 +11,7 @@
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- DIO design with NIC or Etherbone capabilities.
-- This uses the NIC inside the BSP block.
-- DIO design with NIC or Etherbone capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions
-------------------------------------------------------------------------------
...
...
@@ -36,6 +35,7 @@ use work.etherbone_pkg.all;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_dio_pkg
.
all
;
use
work
.
wr_nic_wrapper_pkg
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
...
...
@@ -251,40 +251,7 @@ architecture top of dio_common_top is
dio_int
:
out
std_logic
);
end
component
;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
1
;
-- Number of slaves on the primary wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
2
;
-- Primary Wishbone master(s) offsets
constant
c_WB_MASTER_PCIE
:
integer
:
=
0
;
-- Primary Wishbone slave(s) offsets
constant
c_WB_SLAVE_WRC
:
integer
:
=
0
;
constant
c_WB_SLAVE_DIO
:
integer
:
=
1
;
-- sdb header address on primary crossbar
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00063000"
;
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant
c_wrc_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
constant
c_wr_dio_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_product_manual_sdb
(
x"00000fff"
,
x"00000400"
,
c_xwr_dio_sdb
);
-- Primary wishbone crossbar layout
constant
c_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_wrc_bridge_sdb
,
x"00000000"
),
-- WRPC
c_WB_SLAVE_DIO
=>
f_sdb_embed_bridge
(
c_wr_dio_bridge_sdb
,
x"00040000"
)
-- DIO
);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
...
...
@@ -331,6 +298,7 @@ architecture top of dio_common_top is
attribute
IOB
:
string
;
attribute
IOB
of
wrc_pps_out
:
signal
is
"TRUE"
;
signal
wrc_pps_csync_out
:
std_logic
;
signal
wrc_pps_valid_out
:
std_logic
;
signal
wrc_pps_led
:
std_logic
;
signal
wrc_pps_in
:
std_logic
;
signal
svec_led
:
std_logic_vector
(
15
downto
0
);
...
...
@@ -348,6 +316,19 @@ architecture top of dio_common_top is
signal
vic_vec_int
:
std_logic_vector
(
0
downto
0
);
signal
vic_irq
:
std_logic
;
-- WR Fabric I/F
signal
wrc_wrf_src_out
:
t_wrf_source_out
;
signal
wrc_wrf_src_in
:
t_wrf_source_in
;
signal
wrc_wrf_snk_out
:
t_wrf_sink_out
;
signal
wrc_wrf_snk_in
:
t_wrf_sink_in
;
-- Tx Timestamp
signal
wrc_timestamps_out
:
t_txtsu_timestamp
;
signal
wrc_timestamps_ack_in
:
std_logic
:
=
'1'
;
-- VIC-only signals
signal
vic_only_irqs
:
std_logic_vector
(
3
downto
0
);
begin
-- architecture top
-----------------------------------------------------------------------------
...
...
@@ -359,13 +340,13 @@ begin -- architecture top
g_num_slaves
=>
c_NUM_WB_SLAVES
,
g_registered
=>
TRUE
,
g_wraparound
=>
TRUE
,
g_layout
=>
c_WB_LAYOUT
,
g_layout
=>
f_pick_sdb_layout_for_dio
(
g_dio_mode
)
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
slave_i
=>
cnx_master_out
(
c_NUM_WB_MASTERS
-1
downto
0
)
,
slave_o
=>
cnx_master_in
(
c_NUM_WB_MASTERS
-1
downto
0
)
,
slave_i
=>
cnx_master_out
,
slave_o
=>
cnx_master_in
,
master_i
=>
cnx_slave_out
,
master_o
=>
cnx_slave_in
);
...
...
@@ -464,8 +445,7 @@ begin -- architecture top
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
TRUE
,
g_dpram_initf
=>
g_dpram_initf
,
g_fabric_iface
=>
f_pick_fabric_iface_for_dio
(
g_dio_mode
),
g_vic_irqs
=>
1
)
g_fabric_iface
=>
f_pick_fabric_iface_for_dio
(
g_dio_mode
))
port
map
(
areset_n_i
=>
button1_i
,
areset_edge_n_i
=>
gn_rst_n
,
...
...
@@ -517,22 +497,29 @@ begin -- architecture top
wb_slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_WRC
),
wb_slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_WRC
),
wrf_src_o
=>
wrc_wrf_src_out
,
wrf_src_i
=>
wrc_wrf_src_in
,
wrf_snk_o
=>
wrc_wrf_snk_out
,
wrf_snk_i
=>
wrc_wrf_snk_in
,
abscal_txts_o
=>
wrc_abscal_txts_out
,
abscal_rxts_o
=>
wrc_abscal_rxts_out
,
timestamps_o
=>
wrc_timestamps_out
,
timestamps_ack_i
=>
wrc_timestamps_ack_in
,
pps_ext_i
=>
wrc_pps_in
,
pps_p_o
=>
wrc_pps_out
,
pps_csync_o
=>
wrc_pps_csync_out
,
pps_valid_o
=>
wrc_pps_valid_out
,
pps_led_o
=>
wrc_pps_led
,
led_link_o
=>
led_link_o
,
led_act_o
=>
led_act_o
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_seconds
,
tm_cycles_o
=>
tm_cycles
,
vic_irqs_i
=>
vic_vec_int
,
vic_int_o
=>
vic_irq
);
tm_cycles_o
=>
tm_cycles
);
-- Tristates for SFP EEPROM
sfp_mod_def1_b
<=
'0'
when
sfp_scl_out
=
'0'
else
'Z'
;
...
...
@@ -628,5 +615,56 @@ begin -- architecture top
);
vic_vec_int
(
0
)
<=
dio_int
;
NIC_GEN
:
if
g_dio_mode
=
DIO_NIC
generate
cmp_nic_wrapper
:
wr_nic_wrapper
generic
map
(
g_num_irqs
=>
1
,
g_num_ports
=>
1
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
resetn_i
=>
rst_sys_62m5_n
,
ext_slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_NIC_VIC
),
ext_slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_NIC_VIC
),
nic_snk_i
=>
wrc_wrf_src_out
,
nic_snk_o
=>
wrc_wrf_src_in
,
nic_src_i
=>
wrc_wrf_snk_out
,
nic_src_o
=>
wrc_wrf_snk_in
,
pps_p_i
=>
wrc_pps_csync_out
,
pps_valid_i
=>
wrc_pps_valid_out
,
vic_irqs_i
=>
vic_vec_int
,
vic_int_o
=>
vic_irq
,
txtsu_timestamps_i
(
0
)
=>
wrc_timestamps_out
,
txtsu_timestamps_ack_o
(
0
)
=>
wrc_timestamps_ack_in
);
end
generate
NIC_GEN
;
VIC_ONLY_GEN
:
if
g_dio_mode
=
DIO_ETHERBONE
generate
cmp_vic
:
xwb_vic
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_interrupts
=>
4
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_NIC_VIC
),
slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_NIC_VIC
),
irqs_i
=>
vic_only_irqs
,
irq_master_o
=>
vic_irq
);
-- Reserved
vic_only_irqs
(
0
)
<=
'0'
;
vic_only_irqs
(
1
)
<=
'0'
;
-- PPS
vic_only_irqs
(
2
)
<=
wrc_pps_csync_out
;
-- DIO
vic_only_irqs
(
3
)
<=
vic_vec_int
(
0
);
-- Dummy signals for Fabric and Tx Timestamp ports
wrc_wrf_src_in
<=
c_dummy_src_in
;
wrc_wrf_snk_in
<=
c_dummy_snk_in
;
wrc_timestamps_ack_in
<=
'1'
;
end
generate
VIC_ONLY_GEN
;
end
architecture
top
;
hdl/top/dio-common/dio_common_top_pkg.vhd
View file @
3b614a4b
...
...
@@ -27,12 +27,14 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_dio_pkg
.
all
;
package
dio_common_top_pkg
is
type
t_dio_cfg_mode
is
(
DIO_NIC
,
DIO_ETHERBONE
);
function
f_pick_fabric_iface_for_dio
(
mode
:
t_dio_cfg_mode
)
return
t_board_fabric_iface
;
function
f_pick_sdb_layout_for_dio
(
mode
:
t_dio_cfg_mode
)
return
t_sdb_record_array
;
component
dio_common_top
generic
(
...
...
@@ -194,7 +196,47 @@ package dio_common_top_pkg is
);
end
component
;
-- Number of masters on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
1
;
-- Number of slaves on the primary wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
3
;
-- Primary Wishbone master(s) offsets
constant
c_WB_MASTER_PCIE
:
integer
:
=
0
;
-- Primary Wishbone slave(s) offsets
constant
c_WB_SLAVE_WRC
:
integer
:
=
0
;
constant
c_WB_SLAVE_NIC_VIC
:
integer
:
=
1
;
constant
c_WB_SLAVE_DIO
:
integer
:
=
2
;
-- sdb header address on primary crossbar
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00070000"
;
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant
c_wrc_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
constant
c_nic_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0001ffff"
,
x"00011000"
);
constant
c_wr_dio_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_product_manual_sdb
(
x"00000fff"
,
x"00000400"
,
c_xwr_dio_sdb
);
-- Primary wishbone crossbar layout (NIC)
constant
c_NIC_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_wrc_bridge_sdb
,
x"00000000"
),
-- WRPC
c_WB_SLAVE_NIC_VIC
=>
f_sdb_embed_bridge
(
c_nic_bridge_sdb
,
x"00040000"
),
-- NIC
c_WB_SLAVE_DIO
=>
f_sdb_embed_bridge
(
c_wr_dio_bridge_sdb
,
x"00060000"
)
-- DIO
);
-- Primary wishbone crossbar layout (NIC)
constant
c_VIC_ONLY_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_wrc_bridge_sdb
,
x"00000000"
),
-- WRPC
c_WB_SLAVE_NIC_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00040000"
),
-- VIC
c_WB_SLAVE_DIO
=>
f_sdb_embed_bridge
(
c_wr_dio_bridge_sdb
,
x"00060000"
)
-- DIO
);
end
dio_common_top_pkg
;
package
body
dio_common_top_pkg
is
...
...
@@ -203,9 +245,19 @@ package body dio_common_top_pkg is
return
t_board_fabric_iface
is
begin
case
mode
is
when
DIO_NIC
=>
return
NIC
;
when
DIO_NIC
=>
return
PLAIN
;
when
DIO_ETHERBONE
=>
return
ETHERBONE
;
when
others
=>
return
NIC
;
--by default
when
others
=>
return
PLAIN
;
--by default
end
case
;
end
function
;
function
f_pick_sdb_layout_for_dio
(
mode
:
t_dio_cfg_mode
)
return
t_sdb_record_array
is
begin
case
mode
is
when
DIO_NIC
=>
return
c_NIC_WB_LAYOUT
;
when
DIO_ETHERBONE
=>
return
c_VIC_ONLY_WB_LAYOUT
;
when
others
=>
return
c_NIC_WB_LAYOUT
;
--by default
end
case
;
end
function
;
...
...
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