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FMC DIO 5ch TTL a
Commit 5ae31c31 authored by Javier's avatar Javier Committed by Miguel Jimenez Lopez
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Fist dio-core update from jdiaz

parent 452092a1
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modules/wrsw_dio/wrsw_dio.vhd
View file @ 5ae31c31
......@@ -11,10 +11,10 @@
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: The DIO core allows configuration of each one of the 5 channels of
-- the DIO mezzanine as input or output. For inputs, it provides an accurate UTC
-- time stamp (using UTC from the WRPC, not shown in the diagram) and
-- the DIO mezzanine as input or output. For inputs, it provides an accurate seconds
-- time stamp (using seconds from the WRPC, not shown in the diagram) and
-- a host (PCIe) interrupt via the IRQ Gen block. For outputs, it allows the user
-- to schedule the generation of a pulse at a given future UTC time, or to generate
-- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately.
-------------------------------------------------------------------------------
-- TODO:
......@@ -60,7 +60,7 @@ entity wrsw_dio is
fmc_sda_b : inout std_logic;
tm_time_valid_i : in std_logic;
tm_utc_i : in std_logic_vector(39 downto 0);
tm_seconds_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
TRIG0 : out std_logic_vector(31 downto 0);
......@@ -69,8 +69,8 @@ entity wrsw_dio is
TRIG3 : out std_logic_vector(31 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wb_irq_data_fifo_o : out std_logic
slave_o : out t_wishbone_slave_out
-- wb_irq_data_fifo_o : out std_logic
);
end wrsw_dio;
......@@ -78,20 +78,20 @@ entity wrsw_dio is
architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate UTC time)
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
component dummy_time is
port(
clk_sys : in std_logic;
rst_n : in std_logic;
tm_utc : out std_logic_vector(39 downto 0);
tm_cycles : out std_logic_vector(27 downto 0));
end component;
-- component dummy_time is
-- port(
-- clk_sys : in std_logic;
-- rst_n : in std_logic;
-- tm_utc : out std_logic_vector(39 downto 0);
-- tm_cycles : out std_logic_vector(27 downto 0));
-- end component;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
-- output when the UTC time passed to it through a vector equals a
-- pre-programmed UTC time.
-- output when the seconds time passed to it through a vector equals a
-- pre-programmed seconds time.
-------------------------------------------------------------------------------
component pulse_gen is
generic (
......@@ -146,7 +146,7 @@ architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
-- 1: time given on tm_seconds_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
......@@ -158,7 +158,7 @@ architecture rtl of wrsw_dio is
---------------------------------------------------------------------------
tag_utc_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
-- single-cycle pulse: strobe tag on tag_seconds_o and tag_cycles_o
tag_valid_p1_o : out std_logic
);
end component;
......@@ -184,8 +184,8 @@ architecture rtl of wrsw_dio is
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
......@@ -194,8 +194,8 @@ architecture rtl of wrsw_dio is
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
......@@ -204,8 +204,8 @@ architecture rtl of wrsw_dio is
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
......@@ -214,8 +214,8 @@ architecture rtl of wrsw_dio is
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
......@@ -224,44 +224,54 @@ architecture rtl of wrsw_dio is
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trig0_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trigh0_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trig1_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trigh1_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trig2_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trigh2_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trig3_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trigh3_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trig4_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trigh4_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation'
dio_trig_ena_ena_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation'
dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
......@@ -295,16 +305,16 @@ architecture rtl of wrsw_dio is
signal sda_pad_in, sda_pad_out, sda_pad_oen : std_logic;
-- Pulse generator trigger registers signals
type t_utc_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_seconds_array is array (4 downto 0) of std_logic_vector (39 downto 0);
type t_cycles_array is array (4 downto 0) of std_logic_vector (27 downto 0);
signal trig_utc : t_utc_array;
signal trig_seconds : t_seconds_array;
signal trig_cycles : t_cycles_array;
signal trig_valid_p1 : std_logic_vector (4 downto 0);
signal trig_ready : std_logic_vector (4 downto 0);
signal tag_utc : t_utc_array;
signal tag_seconds : t_seconds_array;
signal tag_cycles : t_cycles_array;
signal tag_valid_p1 : std_logic_vector (4 downto 0);
......@@ -312,21 +322,15 @@ architecture rtl of wrsw_dio is
signal dio_tsf_wr_req : std_logic_vector (4 downto 0);
signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
signal dio_tsf_wr_empty : std_logic_vector (4 downto 0);
signal dio_tsf_tag_utc : t_utc_array;
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_cycles : t_cycles_array;
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
-- Monostable signals
signal dio_puls_inmed_pul_inm_0 : std_logic;
signal dio_puls_inmed_pul_inm_1 : std_logic;
signal dio_puls_inmed_pul_inm_2 : std_logic;
signal dio_puls_inmed_pul_inm_3 : std_logic;
signal dio_puls_inmed_pul_inm_4 : std_logic;
-- DEBUG SIGNALS FOR USING UTC time values from dummy_time instead WRPC
signal tm_utc : std_logic_vector (39 downto 0);
-- DEBUG SIGNALS FOR USING seconds time values from dummy_time instead WRPC
signal tm_seconds : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
-- WB Crossbar
......@@ -345,24 +349,25 @@ architecture rtl of wrsw_dio is
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
-- DIO SIGNAL
signal dio_out : std_logic_vector(4 downto 0);
signal dio_puls_inmed : std_logic_vector(4 downto 0);
-- DIO related signasls
signal dio_monost : std_logic_vector(4 downto 0);
signal dio_prog : std_logic_vector(4 downto 0);
signal dio_puls_inmed : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- rtl
-------------------------------------------------------------------------------
begin
-- Dummy counter for simulationg WRPC utc time
U_dummy: dummy_time
port map(
clk_sys => clk_ref_i,
rst_n => rst_n_i,
tm_utc => tm_utc,
tm_cycles => tm_cycles
);
-- Dummy counter for simulationg WRPC seconds time
-- U_dummy: dummy_time
-- port map(
-- clk_sys => clk_ref_i,
-- rst_n => rst_n_i,
-- tm_utc => tm_utc,
-- tm_cycles => tm_cycles
-- );
------------------------------------------------------------------------------
-- GEN AND STAMPER
......@@ -374,19 +379,21 @@ begin
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_out(i),
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_utc,--tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
pulse_o => dio_prog(i),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(i),
trig_utc_i => trig_utc(i),
trig_utc_i => trig_seconds(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i));
dio_out_o(i) <= dio_puls_inmed(i) when dio_puls_inmed(i) = '1' else dio_out(i);
U_pulse_stamper : pulse_stamper
port map(
......@@ -396,23 +403,18 @@ begin
pulse_a_i => dio_in_i(i),
tm_time_valid_i => '1',--tm_time_valid_i,
tm_utc_i => tm_utc, --tm_utc_i,
tm_cycles_i => tm_cycles, --tm_cycles_i,
tag_utc_o => tag_utc(i),
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_utc, --tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tag_utc_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_p1_o => tag_valid_p1(i));
end generate gen_pulse_modules;
dio_puls_inmed(0) <= dio_puls_inmed_pul_inm_0;
dio_puls_inmed(1) <= dio_puls_inmed_pul_inm_1;
dio_puls_inmed(2) <= dio_puls_inmed_pul_inm_2;
dio_puls_inmed(3) <= dio_puls_inmed_pul_inm_3;
dio_puls_inmed(4) <= dio_puls_inmed_pul_inm_4;
end generate gen_pulse_modules;
------------------------------------------------------------------------------
-- WB ONEWIRE MASTER
......@@ -509,10 +511,9 @@ begin
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
-- DEBUG: BE CAREFULL, dio_out disconected from GPIO because it is used in
-- pulse_gen module!
--dio_out_o(i) <= gpio_out(4*i);
-- END DEBUG
dio_monost(i) <= '1' when dio_puls_inmed(i) = '1' else dio_prog(i);
dio_out_o(i) <= dio_monost(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_oe_n_o(i) <= gpio_out(4*i+1);
dio_term_en_o(i) <= gpio_out(4*i+2);
end generate gen_pio_assignment;
......@@ -526,9 +527,9 @@ begin
--gpio_in(30) <= prsnt_m2c_l;
------------------------------------------------------------------------------
-- WB UTC-BASED PULSE GENERATION & INPUT STAMPING
-- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
------------------------------------------------------------------------------
U_utc_wbslave : wrsw_dio_wb
U_seconds_wbslave : wrsw_dio_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -541,76 +542,84 @@ begin
wb_we_i => cbar_master_out(3).we,
wb_ack_o => cbar_master_in(3).ack,
wb_stall_o => cbar_master_in(3).stall,
wb_int_o => wb_irq_data_fifo_o, --slave_o.int,
wb_int_o => cbar_master_in(3).int,--wb_irq_data_fifo_o, --slave_o.int,
clk_asyn_i => clk_ref_i,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
dio_tsf0_wr_full_o => dio_tsf_wr_full(0),
dio_tsf0_wr_empty_o => dio_tsf_wr_empty(0),
dio_tsf0_tag_utc_i => dio_tsf_tag_utc(0)(31 downto 0),
dio_tsf0_tag_utch_i => dio_tsf_tag_utc(0)(39 downto 32),
dio_tsf0_tag_seconds_i => dio_tsf_tag_seconds(0)(31 downto 0),
dio_tsf0_tag_secondsh_i => dio_tsf_tag_seconds(0)(39 downto 32),
dio_tsf0_tag_cycles_i => dio_tsf_tag_cycles(0),
irq_nempty_0_i => irq_nempty(0),
dio_tsf1_wr_req_i => dio_tsf_wr_req(1),
dio_tsf1_wr_full_o => dio_tsf_wr_full(1),
dio_tsf1_wr_empty_o => dio_tsf_wr_empty(1),
dio_tsf1_tag_utc_i => dio_tsf_tag_utc(1)(31 downto 0),
dio_tsf1_tag_utch_i => dio_tsf_tag_utc(1)(39 downto 32),
dio_tsf1_tag_seconds_i => dio_tsf_tag_seconds(1)(31 downto 0),
dio_tsf1_tag_secondsh_i => dio_tsf_tag_seconds(1)(39 downto 32),
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
dio_tsf2_wr_full_o => dio_tsf_wr_full(2),
dio_tsf2_wr_empty_o => dio_tsf_wr_empty(2),
dio_tsf2_tag_utc_i => dio_tsf_tag_utc(2)(31 downto 0),
dio_tsf2_tag_utch_i => dio_tsf_tag_utc(2)(39 downto 32),
dio_tsf2_tag_seconds_i => dio_tsf_tag_seconds(2)(31 downto 0),
dio_tsf2_tag_secondsh_i => dio_tsf_tag_seconds(2)(39 downto 32),
dio_tsf2_tag_cycles_i => dio_tsf_tag_cycles(2),
irq_nempty_2_i => irq_nempty(2),
dio_tsf3_wr_req_i => dio_tsf_wr_req(3),
dio_tsf3_wr_full_o => dio_tsf_wr_full(3),
dio_tsf3_wr_empty_o => dio_tsf_wr_empty(3),
dio_tsf3_tag_utc_i => dio_tsf_tag_utc(3)(31 downto 0),
dio_tsf3_tag_utch_i => dio_tsf_tag_utc(3)(39 downto 32),
dio_tsf3_tag_seconds_i => dio_tsf_tag_seconds(3)(31 downto 0),
dio_tsf3_tag_secondsh_i => dio_tsf_tag_seconds(3)(39 downto 32),
dio_tsf3_tag_cycles_i => dio_tsf_tag_cycles(3),
irq_nempty_3_i => irq_nempty(3),
dio_tsf4_wr_req_i => dio_tsf_wr_req(4),
dio_tsf4_wr_full_o => dio_tsf_wr_full(4),
dio_tsf4_wr_empty_o => dio_tsf_wr_empty(4),
dio_tsf4_tag_utc_i => dio_tsf_tag_utc(4)(31 downto 0),
dio_tsf4_tag_utch_i => dio_tsf_tag_utc(4)(39 downto 32),
dio_tsf4_tag_seconds_i => dio_tsf_tag_seconds(4)(31 downto 0),
dio_tsf4_tag_secondsh_i => dio_tsf_tag_seconds(4)(39 downto 32),
dio_tsf4_tag_cycles_i => dio_tsf_tag_cycles(4),
irq_nempty_4_i => irq_nempty(4),
dio_trig0_utc_o => trig_utc(0)(31 downto 0),
dio_trigh0_utc_o => trig_utc(0)(39 downto 32),
dio_trig0_seconds_o => trig_seconds(0)(31 downto 0),
dio_trigh0_seconds_o => trig_seconds(0)(39 downto 32),
dio_cyc0_cyc_o => trig_cycles(0),
dio_trig1_utc_o => trig_utc(1)(31 downto 0),
dio_trigh1_utc_o => trig_utc(1)(39 downto 32),
dio_trig1_seconds_o => trig_seconds(1)(31 downto 0),
dio_trigh1_seconds_o => trig_seconds(1)(39 downto 32),
dio_cyc1_cyc_o => trig_cycles(1),
dio_trig2_utc_o => trig_utc(2)(31 downto 0),
dio_trigh2_utc_o => trig_utc(2)(39 downto 32),
dio_trig2_seconds_o => trig_seconds(2)(31 downto 0),
dio_trigh2_seconds_o => trig_seconds(2)(39 downto 32),
dio_cyc2_cyc_o => trig_cycles(2),
dio_trig3_utc_o => trig_utc(3)(31 downto 0),
dio_trigh3_utc_o => trig_utc(3)(39 downto 32),
dio_trig3_seconds_o => trig_seconds(3)(31 downto 0),
dio_trigh3_seconds_o => trig_seconds(3)(39 downto 32),
dio_cyc3_cyc_o => trig_cycles(3),
dio_trig4_utc_o => trig_utc(4)(31 downto 0),
dio_trigh4_utc_o => trig_utc(4)(39 downto 32),
dio_trig4_seconds_o => trig_seconds(4)(31 downto 0),
dio_trigh4_seconds_o => trig_seconds(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4),
dio_trig_ena_ena_o => trig_valid_p1,
dio_trig_ena_rdy_i => trig_ready,
dio_puls_inmed_pul_inm_0_o => dio_puls_inmed_pul_inm_0,
dio_puls_inmed_pul_inm_1_o => dio_puls_inmed_pul_inm_1,
dio_puls_inmed_pul_inm_2_o => dio_puls_inmed_pul_inm_2,
dio_puls_inmed_pul_inm_3_o => dio_puls_inmed_pul_inm_3,
dio_puls_inmed_pul_inm_4_o => dio_puls_inmed_pul_inm_4
dio_out_mode_o => dio_out_mode,
dio_latch_time_ch0_o => trig_valid_p1(0),
dio_latch_time_ch1_o => trig_valid_p1(1),
dio_latch_time_ch2_o => trig_valid_p1(2),
dio_latch_time_ch3_o => trig_valid_p1(3),
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_trig_rdy_i => trig_ready,
dio_puls_inmed_pul_inm_0_o => dio_puls_inmed(0),
dio_puls_inmed_pul_inm_1_o => dio_puls_inmed(1),
dio_puls_inmed_pul_inm_2_o => dio_puls_inmed(2),
dio_puls_inmed_pul_inm_3_o => dio_puls_inmed(3),
dio_puls_inmed_pul_inm_4_o => dio_puls_inmed(4)
);
-----------------------------------------------------------------------------------
......@@ -620,14 +629,14 @@ begin
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
-- TRIG1(0) <= cbar_master_in(3).int;
-- TRIG2 <= tm_utc(31 downto 0);
TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
-- TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-- UTC timestamped FIFO-no-empty interrupts
-- seconds timestamped FIFO-no-empty interrupts
irq_fifos : for i in 0 to 4 generate
irq_nempty(i) <= not dio_tsf_wr_empty(i);
......@@ -636,12 +645,12 @@ begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dio_tsf_wr_req(i) <= '0';
dio_tsf_tag_utc(i) <= (others => '0');
dio_tsf_tag_seconds(i) <= (others => '0');
dio_tsf_tag_cycles(i) <= (others => '0');
else
if ((tag_valid_p1(i) = '1') AND (dio_tsf_wr_full(i)='0')) then
dio_tsf_wr_req(i) <='1';
dio_tsf_tag_utc(i) <=tag_utc(i);
dio_tsf_tag_seconds(i) <=tag_seconds(i);
dio_tsf_tag_cycles(i) <=tag_cycles(i);
else
dio_tsf_wr_req(i) <='0';
......
modules/wrsw_dio/wrsw_dio.wb
View file @ 5ae31c31
......@@ -18,24 +18,24 @@ peripheral {
prefix = "tsf0";
name = "Timestamp FIFO 0";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_utc - utc time in seconds\
- tag_seconds - seconds time\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "UTC time";
descritpion = "UTC time in seconds (LSB)";
prefix = "tag_utc";
name = "seconds time";
descritpion = "seconds time (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "UTC time H";
descritpion = "UTC time in seconds (MSB)";
prefix = "tag_utcH";
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
......@@ -66,24 +66,24 @@ peripheral {
prefix = "tsf1";
name = "Timestamp FIFO 1";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_utc - utc time in seconds\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "UTC time";
descritpion = "UTC time in seconds (LSB)";
prefix = "tag_utc";
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "UTC time H";
descritpion = "UTC time in seconds (MSB)";
prefix = "tag_utcH";
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
......@@ -114,24 +114,24 @@ peripheral {
prefix = "tsf2";
name = "Timestamp FIFO 2";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_utc - utc time in seconds\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "UTC time";
descritpion = "UTC time in seconds (LSB)";
prefix = "tag_utc";
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "UTC time H";
descritpion = "UTC time in seconds (MSB)";
prefix = "tag_utcH";
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
......@@ -162,24 +162,24 @@ peripheral {
prefix = "tsf3";
name = "Timestamp FIFO 3";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_utc - utc time in seconds\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "UTC time";
descritpion = "UTC time in seconds (LSB)";
prefix = "tag_utc";
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "UTC time H";
descritpion = "UTC time in seconds (MSB)";
prefix = "tag_utcH";
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
......@@ -210,24 +210,24 @@ peripheral {
prefix = "tsf4";
name = "Timestamp FIFO 4";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_utc - utc time in seconds\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "UTC time";
descritpion = "UTC time in seconds (LSB)";
prefix = "tag_utc";
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "UTC time H";
descritpion = "UTC time in seconds (MSB)";
prefix = "tag_utcH";
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
......@@ -254,16 +254,16 @@ peripheral {
-- REGISTERS FOR OUTPUT EVENT TIME-BASED TRIGGER
-------------------------------------------------
-- DIO CHANNEL 0: UTC value . Readable-writable the bus, readble from the device.
-- DIO CHANNEL 0: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 0 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (LSB).";
name = "fmc-dio 0 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig0";
field {
name = "utc field";
name = "seconds field";
description = "TBD";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -272,14 +272,14 @@ peripheral {
};
reg {
name = "fmc-dio 0 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (MSB).";
name = "fmc-dio 0 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH0";
field {
name = "utc field";
name = "seconds field";
description = "Number of seconds";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
......@@ -303,16 +303,16 @@ peripheral {
};
};
-- DIO CHANNEL 1: UTC value . Readable-writable the bus, readble from the device.
-- DIO CHANNEL 1: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 1 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (LSB).";
name = "fmc-dio 1 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig1";
field {
name = "utc field";
name = "seconds field";
description = "TBD";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -321,14 +321,14 @@ peripheral {
};
reg {
name = "fmc-dio 1 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (MSB).";
name = "fmc-dio 1 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH1";
field {
name = "utc field";
name = "seconds field";
description = "Number of seconds";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
......@@ -352,16 +352,16 @@ peripheral {
};
};
-- DIO CHANNEL 2: UTC value . Readable-writable the bus, readble from the device.
-- DIO CHANNEL 2: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 2 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (LSB).";
name = "fmc-dio 2 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig2";
field {
name = "utc field";
name = "seconds field";
description = "TBD";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -370,14 +370,14 @@ peripheral {
};
reg {
name = "fmc-dio 2 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (MSB).";
name = "fmc-dio 2 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH2";
field {
name = "utc field";
name = "seconds field";
description = "Number of seconds";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
......@@ -401,16 +401,16 @@ peripheral {
};
};
-- DIO CHANNEL 3: UTC value . Readable-writable the bus, readble from the device.
-- DIO CHANNEL 3: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 3 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (LSB).";
name = "fmc-dio 3 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig3";
field {
name = "utc field";
name = "seconds field";
description = "TBD";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -419,14 +419,14 @@ peripheral {
};
reg {
name = "fmc-dio 3 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (MSB).";
name = "fmc-dio 3 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH3";
field {
name = "utc field";
name = "seconds field";
description = "Number of seconds";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
......@@ -450,16 +450,16 @@ peripheral {
};
};
-- DIO CHANNEL 4: UTC value . Readable-writable the bus, readble from the device.
-- DIO CHANNEL 4: seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 4 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (LSB).";
name = "fmc-dio 4 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig4";
field {
name = "utc field";
name = "seconds field";
description = "TBD";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -468,14 +468,14 @@ peripheral {
};
reg {
name = "fmc-dio 4 UTC-based trigger for pulse generation";
description = "trigger utc value for dio output (MSB).";
name = "fmc-dio 4 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH4";
field {
name = "utc field";
name = "seconds field";
description = "Number of seconds";
prefix = "utc";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
......@@ -500,16 +500,16 @@ peripheral {
};
-- UTC trigger enable value. Readable-writable the bus, readble from the device.
-- Monostable/Programmable output or GPIO selection
reg {
name = "FMC-DIO UTC-based trigger Enable-register for pulse generation";
description = "enable register for using using utc trigger values for dio output.";
prefix = "trig_ena";
name = "FMC-DIO output configuration register. ";
description = "It allows to choose a Monostable/programmable output or a standard GPIO output.";
prefix = "out";
field {
name = "trig_enable field";
description = "TBD";
prefix = "ena";
name = "outmode";
description = "1 for programmable, 0 for GPIO output mode";
prefix = "mode";
type = SLV;
size = 5;
access_bus = READ_WRITE;
......@@ -517,11 +517,49 @@ peripheral {
};
};
-- UTC trigger ready value. Readable-writable the bus, writable from the device.
-- Single-cycle strobe signal to latch the second/cycles values of the programamble output
reg {
name = "FMC-DIO UTC-based trigger ready informaton for pulse generation";
description = "ready state, waiting trigger commands for dio output.";
prefix = "trig_ena";
name = "Time-programmable output strobe signal";
description = "It is used to latch second/cycles values generation just 1 clock cycle output ";
prefix = "latch";
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch0";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch1";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch2";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch3";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch4";
type = MONOSTABLE;
};
};
-- seconds trigger ready value. Readable-writable the bus, writable from the device.
reg {
name = "FMC-DIO seconds-based trigger is ready to accept a new trigger generation request";
description = "ready state, waiting new trigger commands for dio output.";
prefix = "trig";
field {
name = "trig_rdy field";
......@@ -576,7 +614,6 @@ peripheral {
type = MONOSTABLE;
clock = "clk_asyn_i";
};
};
};
modules/wrsw_dio/wrsw_dio_wb.htm
View file @ 5ae31c31
......@@ -34,48 +34,49 @@
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">fmc-dio 0 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">fmc-dio 0 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">fmc-dio 0 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">fmc-dio 0 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">fmc-dio 0 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">fmc-dio 1 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">fmc-dio 1 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">fmc-dio 1 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">fmc-dio 1 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">fmc-dio 1 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">fmc-dio 2 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">fmc-dio 2 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">fmc-dio 2 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">fmc-dio 2 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">fmc-dio 2 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">fmc-dio 3 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">fmc-dio 3 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">fmc-dio 3 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">fmc-dio 3 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">fmc-dio 3 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">fmc-dio 4 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">fmc-dio 4 UTC-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">fmc-dio 4 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">fmc-dio 4 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">fmc-dio 4 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO UTC-based trigger Enable-register for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">FMC-DIO UTC-based trigger ready informaton for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Pulse generate immediately</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Interrupt status register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">FIFO 'Timestamp FIFO 0' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">FIFO 'Timestamp FIFO 0' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">FIFO 'Timestamp FIFO 0' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">FIFO 'Timestamp FIFO 0' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">FIFO 'Timestamp FIFO 1' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">FIFO 'Timestamp FIFO 1' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">FIFO 'Timestamp FIFO 1' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">FIFO 'Timestamp FIFO 1' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">FIFO 'Timestamp FIFO 2' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">FIFO 'Timestamp FIFO 2' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">FIFO 'Timestamp FIFO 2' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">FIFO 'Timestamp FIFO 2' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">FIFO 'Timestamp FIFO 3' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">FIFO 'Timestamp FIFO 3' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">FIFO 'Timestamp FIFO 3' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">FIFO 'Timestamp FIFO 3' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">FIFO 'Timestamp FIFO 4' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">FIFO 'Timestamp FIFO 4' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">FIFO 'Timestamp FIFO 4' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">FIFO 'Timestamp FIFO 4' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO output configuration register. </a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Time-programmable output strobe signal</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">FMC-DIO seconds-based trigger is ready to accept a new trigger generation request</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Pulse generate immediately</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Interrupt status register</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">FIFO 'Timestamp FIFO 0' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">FIFO 'Timestamp FIFO 0' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">FIFO 'Timestamp FIFO 0' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">FIFO 'Timestamp FIFO 0' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">FIFO 'Timestamp FIFO 1' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">FIFO 'Timestamp FIFO 1' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">FIFO 'Timestamp FIFO 1' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">FIFO 'Timestamp FIFO 1' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">FIFO 'Timestamp FIFO 2' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">FIFO 'Timestamp FIFO 2' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">FIFO 'Timestamp FIFO 2' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">FIFO 'Timestamp FIFO 2' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">FIFO 'Timestamp FIFO 3' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">FIFO 'Timestamp FIFO 3' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">FIFO 'Timestamp FIFO 3' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">FIFO 'Timestamp FIFO 3' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">FIFO 'Timestamp FIFO 4' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">FIFO 'Timestamp FIFO 4' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">FIFO 'Timestamp FIFO 4' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">FIFO 'Timestamp FIFO 4' control/status register</a></span><br/>
<span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/>
<span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">dio fifo not-empty 0</a></span><br/>
<span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">dio fifo not-empty 1</a></span><br/>
......@@ -109,7 +110,7 @@ C prefix
REG
</td>
<td >
<A href="#TRIG0">fmc-dio 0 UTC-based trigger for pulse generation</a>
<A href="#TRIG0">fmc-dio 0 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trig0
......@@ -126,7 +127,7 @@ TRIG0
REG
</td>
<td >
<A href="#TRIGH0">fmc-dio 0 UTC-based trigger for pulse generation</a>
<A href="#TRIGH0">fmc-dio 0 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trigh0
......@@ -160,7 +161,7 @@ CYC0
REG
</td>
<td >
<A href="#TRIG1">fmc-dio 1 UTC-based trigger for pulse generation</a>
<A href="#TRIG1">fmc-dio 1 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trig1
......@@ -177,7 +178,7 @@ TRIG1
REG
</td>
<td >
<A href="#TRIGH1">fmc-dio 1 UTC-based trigger for pulse generation</a>
<A href="#TRIGH1">fmc-dio 1 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trigh1
......@@ -211,7 +212,7 @@ CYC1
REG
</td>
<td >
<A href="#TRIG2">fmc-dio 2 UTC-based trigger for pulse generation</a>
<A href="#TRIG2">fmc-dio 2 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trig2
......@@ -228,7 +229,7 @@ TRIG2
REG
</td>
<td >
<A href="#TRIGH2">fmc-dio 2 UTC-based trigger for pulse generation</a>
<A href="#TRIGH2">fmc-dio 2 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trigh2
......@@ -262,7 +263,7 @@ CYC2
REG
</td>
<td >
<A href="#TRIG3">fmc-dio 3 UTC-based trigger for pulse generation</a>
<A href="#TRIG3">fmc-dio 3 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trig3
......@@ -279,7 +280,7 @@ TRIG3
REG
</td>
<td >
<A href="#TRIGH3">fmc-dio 3 UTC-based trigger for pulse generation</a>
<A href="#TRIGH3">fmc-dio 3 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trigh3
......@@ -313,7 +314,7 @@ CYC3
REG
</td>
<td >
<A href="#TRIG4">fmc-dio 4 UTC-based trigger for pulse generation</a>
<A href="#TRIG4">fmc-dio 4 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trig4
......@@ -330,7 +331,7 @@ TRIG4
REG
</td>
<td >
<A href="#TRIGH4">fmc-dio 4 UTC-based trigger for pulse generation</a>
<A href="#TRIGH4">fmc-dio 4 seconds-based trigger for pulse generation</a>
</td>
<td class="td_code">
dio_trigh4
......@@ -364,13 +365,13 @@ CYC4
REG
</td>
<td >
<A href="#TRIG_ENA">FMC-DIO UTC-based trigger Enable-register for pulse generation</a>
<A href="#OUT">FMC-DIO output configuration register. </a>
</td>
<td class="td_code">
dio_trig_ena
dio_out
</td>
<td class="td_code">
TRIG_ENA
OUT
</td>
</tr>
<tr class="tr_odd">
......@@ -381,13 +382,13 @@ TRIG_ENA
REG
</td>
<td >
<A href="#TRIG_ENA">FMC-DIO UTC-based trigger ready informaton for pulse generation</a>
<A href="#LATCH">Time-programmable output strobe signal</a>
</td>
<td class="td_code">
dio_trig_ena
dio_latch
</td>
<td class="td_code">
TRIG_ENA
LATCH
</td>
</tr>
<tr class="tr_even">
......@@ -398,6 +399,23 @@ TRIG_ENA
REG
</td>
<td >
<A href="#TRIG">FMC-DIO seconds-based trigger is ready to accept a new trigger generation request</a>
</td>
<td class="td_code">
dio_trig
</td>
<td class="td_code">
TRIG
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x12
</td>
<td >
REG
</td>
<td >
<A href="#PULS_INMED">Pulse generate immediately</a>
</td>
<td class="td_code">
......@@ -407,7 +425,7 @@ dio_puls_inmed
PULS_INMED
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x18
</td>
......@@ -424,7 +442,7 @@ dio_eic_idr
EIC_IDR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x19
</td>
......@@ -441,7 +459,7 @@ dio_eic_ier
EIC_IER
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1a
</td>
......@@ -458,7 +476,7 @@ dio_eic_imr
EIC_IMR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1b
</td>
......@@ -475,7 +493,7 @@ dio_eic_isr
EIC_ISR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1c
</td>
......@@ -492,7 +510,7 @@ dio_tsf0_r0
TSF0_R0
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1d
</td>
......@@ -509,7 +527,7 @@ dio_tsf0_r1
TSF0_R1
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1e
</td>
......@@ -526,7 +544,7 @@ dio_tsf0_r2
TSF0_R2
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1f
</td>
......@@ -543,7 +561,7 @@ dio_tsf0_csr
TSF0_CSR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x20
</td>
......@@ -560,7 +578,7 @@ dio_tsf1_r0
TSF1_R0
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x21
</td>
......@@ -577,7 +595,7 @@ dio_tsf1_r1
TSF1_R1
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x22
</td>
......@@ -594,7 +612,7 @@ dio_tsf1_r2
TSF1_R2
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x23
</td>
......@@ -611,7 +629,7 @@ dio_tsf1_csr
TSF1_CSR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x24
</td>
......@@ -628,7 +646,7 @@ dio_tsf2_r0
TSF2_R0
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x25
</td>
......@@ -645,7 +663,7 @@ dio_tsf2_r1
TSF2_R1
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x26
</td>
......@@ -662,7 +680,7 @@ dio_tsf2_r2
TSF2_R2
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x27
</td>
......@@ -679,7 +697,7 @@ dio_tsf2_csr
TSF2_CSR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x28
</td>
......@@ -696,7 +714,7 @@ dio_tsf3_r0
TSF3_R0
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x29
</td>
......@@ -713,7 +731,7 @@ dio_tsf3_r1
TSF3_R1
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x2a
</td>
......@@ -730,7 +748,7 @@ dio_tsf3_r2
TSF3_R2
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x2b
</td>
......@@ -747,7 +765,7 @@ dio_tsf3_csr
TSF3_CSR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x2c
</td>
......@@ -764,7 +782,7 @@ dio_tsf4_r0
TSF4_R0
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x2d
</td>
......@@ -781,7 +799,7 @@ dio_tsf4_r1
TSF4_R1
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x2e
</td>
......@@ -798,7 +816,7 @@ dio_tsf4_r2
TSF4_R2
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x2f
</td>
......@@ -898,7 +916,7 @@ wb_dat_o[31:0]
</td>
<td class="td_pblock_right">
dio_tsf0_tag_utc_i[31:0]
dio_tsf0_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -915,7 +933,7 @@ wb_cyc_i
</td>
<td class="td_pblock_right">
dio_tsf0_tag_utch_i[7:0]
dio_tsf0_tag_secondsh_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1085,7 +1103,7 @@ dio_tsf1_wr_empty_o
</td>
<td class="td_pblock_right">
dio_tsf1_tag_utc_i[31:0]
dio_tsf1_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1102,7 +1120,7 @@ dio_tsf1_tag_utc_i[31:0]
</td>
<td class="td_pblock_right">
dio_tsf1_tag_utch_i[7:0]
dio_tsf1_tag_secondsh_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1272,7 +1290,7 @@ dio_tsf2_wr_empty_o
</td>
<td class="td_pblock_right">
dio_tsf2_tag_utc_i[31:0]
dio_tsf2_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1289,7 +1307,7 @@ dio_tsf2_tag_utc_i[31:0]
</td>
<td class="td_pblock_right">
dio_tsf2_tag_utch_i[7:0]
dio_tsf2_tag_secondsh_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1459,7 +1477,7 @@ dio_tsf3_wr_empty_o
</td>
<td class="td_pblock_right">
dio_tsf3_tag_utc_i[31:0]
dio_tsf3_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1476,7 +1494,7 @@ dio_tsf3_tag_utc_i[31:0]
</td>
<td class="td_pblock_right">
dio_tsf3_tag_utch_i[7:0]
dio_tsf3_tag_secondsh_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1646,7 +1664,7 @@ dio_tsf4_wr_empty_o
</td>
<td class="td_pblock_right">
dio_tsf4_tag_utc_i[31:0]
dio_tsf4_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1663,7 +1681,7 @@ dio_tsf4_tag_utc_i[31:0]
</td>
<td class="td_pblock_right">
dio_tsf4_tag_utch_i[7:0]
dio_tsf4_tag_secondsh_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1765,7 +1783,7 @@ irq_nempty_4_i
</td>
<td class="td_pblock_right">
<b>fmc-dio 0 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 0 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -1782,7 +1800,7 @@ irq_nempty_4_i
</td>
<td class="td_pblock_right">
dio_trig0_utc_o[31:0]
dio_trig0_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1816,7 +1834,7 @@ dio_trig0_utc_o[31:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 0 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 0 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -1833,7 +1851,7 @@ dio_trig0_utc_o[31:0]
</td>
<td class="td_pblock_right">
dio_trigh0_utc_o[7:0]
dio_trigh0_seconds_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1918,7 +1936,7 @@ dio_cyc0_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 1 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 1 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -1935,7 +1953,7 @@ dio_cyc0_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_trig1_utc_o[31:0]
dio_trig1_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1969,7 +1987,7 @@ dio_trig1_utc_o[31:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 1 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 1 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -1986,7 +2004,7 @@ dio_trig1_utc_o[31:0]
</td>
<td class="td_pblock_right">
dio_trigh1_utc_o[7:0]
dio_trigh1_seconds_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2071,7 +2089,7 @@ dio_cyc1_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 2 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 2 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2088,7 +2106,7 @@ dio_cyc1_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_trig2_utc_o[31:0]
dio_trig2_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2122,7 +2140,7 @@ dio_trig2_utc_o[31:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 2 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 2 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2139,7 +2157,7 @@ dio_trig2_utc_o[31:0]
</td>
<td class="td_pblock_right">
dio_trigh2_utc_o[7:0]
dio_trigh2_seconds_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2224,7 +2242,7 @@ dio_cyc2_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 3 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 3 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2241,7 +2259,7 @@ dio_cyc2_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_trig3_utc_o[31:0]
dio_trig3_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2275,7 +2293,7 @@ dio_trig3_utc_o[31:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 3 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 3 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2292,7 +2310,7 @@ dio_trig3_utc_o[31:0]
</td>
<td class="td_pblock_right">
dio_trigh3_utc_o[7:0]
dio_trigh3_seconds_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2377,7 +2395,7 @@ dio_cyc3_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 4 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 4 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2394,7 +2412,7 @@ dio_cyc3_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_trig4_utc_o[31:0]
dio_trig4_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2428,7 +2446,7 @@ dio_trig4_utc_o[31:0]
</td>
<td class="td_pblock_right">
<b>fmc-dio 4 UTC-based trigger for pulse generation:</b>
<b>fmc-dio 4 seconds-based trigger for pulse generation:</b>
</td>
<td class="td_arrow_right">
......@@ -2445,7 +2463,7 @@ dio_trig4_utc_o[31:0]
</td>
<td class="td_pblock_right">
dio_trigh4_utc_o[7:0]
dio_trigh4_seconds_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2530,7 +2548,7 @@ dio_cyc4_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>FMC-DIO UTC-based trigger Enable-register for pulse generation:</b>
<b>FMC-DIO output configuration register. :</b>
</td>
<td class="td_arrow_right">
......@@ -2547,7 +2565,7 @@ dio_cyc4_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_trig_ena_ena_o[4:0]
dio_out_mode_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2581,7 +2599,7 @@ dio_trig_ena_ena_o[4:0]
</td>
<td class="td_pblock_right">
<b>FMC-DIO UTC-based trigger ready informaton for pulse generation:</b>
<b>Time-programmable output strobe signal:</b>
</td>
<td class="td_arrow_right">
......@@ -2598,7 +2616,126 @@ dio_trig_ena_ena_o[4:0]
</td>
<td class="td_pblock_right">
dio_trig_ena_rdy_i[4:0]
dio_latch_time_ch0_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_latch_time_ch1_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_latch_time_ch2_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_latch_time_ch3_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_latch_time_ch4_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FMC-DIO seconds-based trigger is ready to accept a new trigger generation request:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_trig_rdy_i[4:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -3237,7 +3374,7 @@ dio_puls_inmed_pul_inm_4_o
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="TRIG0"></a>
<h3><a name="sect_3_1">3.1. fmc-dio 0 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_1">3.1. fmc-dio 0 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3273,7 +3410,7 @@ TRIG0
</tr>
</table>
<p>
trigger utc value for dio output (LSB).
trigger seconds value for dio output (LSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -3304,7 +3441,7 @@ trigger utc value for dio output (LSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[31:24]
SECONDS[31:24]
</td>
<td >
......@@ -3358,7 +3495,7 @@ UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[23:16]
SECONDS[23:16]
</td>
<td >
......@@ -3412,7 +3549,7 @@ UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[15:8]
SECONDS[15:8]
</td>
<td >
......@@ -3466,7 +3603,7 @@ UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -3493,12 +3630,12 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>TBD
</ul>
<a name="TRIGH0"></a>
<h3><a name="sect_3_2">3.2. fmc-dio 0 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_2">3.2. fmc-dio 0 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3534,7 +3671,7 @@ TRIGH0
</tr>
</table>
<p>
trigger utc value for dio output (MSB).
trigger seconds value for dio output (MSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -3727,7 +3864,7 @@ trigger utc value for dio output (MSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -3754,8 +3891,8 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>Number of seconds
</ul>
<a name="CYC0"></a>
......@@ -4020,7 +4157,7 @@ CYC
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="TRIG1"></a>
<h3><a name="sect_3_4">3.4. fmc-dio 1 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_4">3.4. fmc-dio 1 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4056,7 +4193,7 @@ TRIG1
</tr>
</table>
<p>
trigger utc value for dio output (LSB).
trigger seconds value for dio output (LSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -4087,7 +4224,7 @@ trigger utc value for dio output (LSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[31:24]
SECONDS[31:24]
</td>
<td >
......@@ -4141,7 +4278,7 @@ UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[23:16]
SECONDS[23:16]
</td>
<td >
......@@ -4195,7 +4332,7 @@ UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[15:8]
SECONDS[15:8]
</td>
<td >
......@@ -4249,7 +4386,7 @@ UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -4276,12 +4413,12 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>TBD
</ul>
<a name="TRIGH1"></a>
<h3><a name="sect_3_5">3.5. fmc-dio 1 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_5">3.5. fmc-dio 1 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4317,7 +4454,7 @@ TRIGH1
</tr>
</table>
<p>
trigger utc value for dio output (MSB).
trigger seconds value for dio output (MSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -4510,7 +4647,7 @@ trigger utc value for dio output (MSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -4537,8 +4674,8 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>Number of seconds
</ul>
<a name="CYC1"></a>
......@@ -4803,7 +4940,7 @@ CYC
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="TRIG2"></a>
<h3><a name="sect_3_7">3.7. fmc-dio 2 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_7">3.7. fmc-dio 2 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4839,7 +4976,7 @@ TRIG2
</tr>
</table>
<p>
trigger utc value for dio output (LSB).
trigger seconds value for dio output (LSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -4870,7 +5007,7 @@ trigger utc value for dio output (LSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[31:24]
SECONDS[31:24]
</td>
<td >
......@@ -4924,7 +5061,7 @@ UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[23:16]
SECONDS[23:16]
</td>
<td >
......@@ -4978,7 +5115,7 @@ UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[15:8]
SECONDS[15:8]
</td>
<td >
......@@ -5032,7 +5169,7 @@ UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -5059,12 +5196,12 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>TBD
</ul>
<a name="TRIGH2"></a>
<h3><a name="sect_3_8">3.8. fmc-dio 2 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_8">3.8. fmc-dio 2 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5100,7 +5237,7 @@ TRIGH2
</tr>
</table>
<p>
trigger utc value for dio output (MSB).
trigger seconds value for dio output (MSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -5293,7 +5430,7 @@ trigger utc value for dio output (MSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -5320,8 +5457,8 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>Number of seconds
</ul>
<a name="CYC2"></a>
......@@ -5586,7 +5723,7 @@ CYC
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="TRIG3"></a>
<h3><a name="sect_3_10">3.10. fmc-dio 3 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_10">3.10. fmc-dio 3 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5622,7 +5759,7 @@ TRIG3
</tr>
</table>
<p>
trigger utc value for dio output (LSB).
trigger seconds value for dio output (LSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -5653,7 +5790,7 @@ trigger utc value for dio output (LSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[31:24]
SECONDS[31:24]
</td>
<td >
......@@ -5707,7 +5844,7 @@ UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[23:16]
SECONDS[23:16]
</td>
<td >
......@@ -5761,7 +5898,7 @@ UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[15:8]
SECONDS[15:8]
</td>
<td >
......@@ -5815,7 +5952,7 @@ UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -5842,12 +5979,12 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>TBD
</ul>
<a name="TRIGH3"></a>
<h3><a name="sect_3_11">3.11. fmc-dio 3 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_11">3.11. fmc-dio 3 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5883,7 +6020,7 @@ TRIGH3
</tr>
</table>
<p>
trigger utc value for dio output (MSB).
trigger seconds value for dio output (MSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6076,7 +6213,7 @@ trigger utc value for dio output (MSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -6103,8 +6240,8 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>Number of seconds
</ul>
<a name="CYC3"></a>
......@@ -6369,7 +6506,7 @@ CYC
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="TRIG4"></a>
<h3><a name="sect_3_13">3.13. fmc-dio 4 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_13">3.13. fmc-dio 4 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6405,7 +6542,7 @@ TRIG4
</tr>
</table>
<p>
trigger utc value for dio output (LSB).
trigger seconds value for dio output (LSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6436,7 +6573,7 @@ trigger utc value for dio output (LSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[31:24]
SECONDS[31:24]
</td>
<td >
......@@ -6490,7 +6627,7 @@ UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[23:16]
SECONDS[23:16]
</td>
<td >
......@@ -6544,7 +6681,7 @@ UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[15:8]
SECONDS[15:8]
</td>
<td >
......@@ -6598,7 +6735,7 @@ UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -6625,12 +6762,12 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>TBD
</ul>
<a name="TRIGH4"></a>
<h3><a name="sect_3_14">3.14. fmc-dio 4 UTC-based trigger for pulse generation</a></h3>
<h3><a name="sect_3_14">3.14. fmc-dio 4 seconds-based trigger for pulse generation</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6666,7 +6803,7 @@ TRIGH4
</tr>
</table>
<p>
trigger utc value for dio output (MSB).
trigger seconds value for dio output (MSB).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6859,7 +6996,7 @@ trigger utc value for dio output (MSB).
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
UTC[7:0]
SECONDS[7:0]
</td>
<td >
......@@ -6886,8 +7023,8 @@ UTC[7:0]
</table>
<ul>
<li><b>
UTC
</b>[<i>read/write</i>]: utc field
SECONDS
</b>[<i>read/write</i>]: seconds field
<br>Number of seconds
</ul>
<a name="CYC4"></a>
......@@ -7151,15 +7288,15 @@ CYC
</b>[<i>read/write</i>]: cycles field
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="TRIG_ENA"></a>
<h3><a name="sect_3_16">3.16. FMC-DIO UTC-based trigger Enable-register for pulse generation</a></h3>
<a name="OUT"></a>
<h3><a name="sect_3_16">3.16. FMC-DIO output configuration register. </a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dio_trig_ena
dio_out
</td>
</tr>
<tr>
......@@ -7175,7 +7312,7 @@ dio_trig_ena
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_ENA
OUT
</td>
</tr>
<tr>
......@@ -7188,7 +7325,7 @@ TRIG_ENA
</tr>
</table>
<p>
enable register for using using utc trigger values for dio output.
It allows to choose a Monostable/programmable output or a standard GPIO output.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7390,7 +7527,7 @@ enable register for using using utc trigger values for dio output.
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
ENA[4:0]
MODE[4:0]
</td>
<td >
......@@ -7408,19 +7545,19 @@ ENA[4:0]
</table>
<ul>
<li><b>
ENA
</b>[<i>read/write</i>]: trig_enable field
<br>TBD
MODE
</b>[<i>read/write</i>]: outmode
<br>1 for programmable, 0 for GPIO output mode
</ul>
<a name="TRIG_ENA"></a>
<h3><a name="sect_3_17">3.17. FMC-DIO UTC-based trigger ready informaton for pulse generation</a></h3>
<a name="LATCH"></a>
<h3><a name="sect_3_17">3.17. Time-programmable output strobe signal</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dio_trig_ena
dio_latch
</td>
</tr>
<tr>
......@@ -7436,7 +7573,7 @@ dio_trig_ena
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_ENA
LATCH
</td>
</tr>
<tr>
......@@ -7449,7 +7586,284 @@ TRIG_ENA
</tr>
</table>
<p>
ready state, waiting trigger commands for dio output.
It is used to latch second/cycles values generation just 1 clock cycle output
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME_CH4
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME_CH3
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME_CH2
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME_CH1
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME_CH0
</td>
</tr>
</table>
<ul>
<li><b>
TIME_CH0
</b>[<i>write-only</i>]: Sincle-cycle strobe
<br>It generates a one-clock cycle pulse for programmable time latching
<li><b>
TIME_CH1
</b>[<i>write-only</i>]: Sincle-cycle strobe
<br>It generates a one-clock cycle pulse for programmable time latching
<li><b>
TIME_CH2
</b>[<i>write-only</i>]: Sincle-cycle strobe
<br>It generates a one-clock cycle pulse for programmable time latching
<li><b>
TIME_CH3
</b>[<i>write-only</i>]: Sincle-cycle strobe
<br>It generates a one-clock cycle pulse for programmable time latching
<li><b>
TIME_CH4
</b>[<i>write-only</i>]: Sincle-cycle strobe
<br>It generates a one-clock cycle pulse for programmable time latching
</ul>
<a name="TRIG"></a>
<h3><a name="sect_3_18">3.18. FMC-DIO seconds-based trigger is ready to accept a new trigger generation request</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dio_trig
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x11
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x44
</td>
</tr>
</table>
<p>
ready state, waiting new trigger commands for dio output.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7674,7 +8088,7 @@ RDY
<br>TBD
</ul>
<a name="PULS_INMED"></a>
<h3><a name="sect_3_18">3.18. Pulse generate immediately</a></h3>
<h3><a name="sect_3_19">3.19. Pulse generate immediately</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -7689,7 +8103,7 @@ dio_puls_inmed
<b>HW address: </b>
</td>
<td class="td_code">
0x11
0x12
</td>
</tr>
<tr>
......@@ -7705,7 +8119,7 @@ PULS_INMED
<b>C offset: </b>
</td>
<td class="td_code">
0x44
0x48
</td>
</tr>
</table>
......@@ -7951,7 +8365,7 @@ PUL_INM_4
<br>It generates a pulse
</ul>
<a name="EIC_IDR"></a>
<h3><a name="sect_3_19">3.19. Interrupt disable register</a></h3>
<h3><a name="sect_3_20">3.20. Interrupt disable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8228,7 +8642,7 @@ NEMPTY_4
<br>write 1: disable interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul>
<a name="EIC_IER"></a>
<h3><a name="sect_3_20">3.20. Interrupt enable register</a></h3>
<h3><a name="sect_3_21">3.21. Interrupt enable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8505,7 +8919,7 @@ NEMPTY_4
<br>write 1: enable interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul>
<a name="EIC_IMR"></a>
<h3><a name="sect_3_21">3.21. Interrupt mask register</a></h3>
<h3><a name="sect_3_22">3.22. Interrupt mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8782,7 +9196,7 @@ NEMPTY_4
<br>read 1: interrupt 'dio fifo not-empty 4' is enabled<br>read 0: interrupt 'dio fifo not-empty 4' is disabled
</ul>
<a name="EIC_ISR"></a>
<h3><a name="sect_3_22">3.22. Interrupt status register</a></h3>
<h3><a name="sect_3_23">3.23. Interrupt status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9059,7 +9473,7 @@ NEMPTY_4
<br>read 1: interrupt 'dio fifo not-empty 4' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul>
<a name="TSF0_R0"></a>
<h3><a name="sect_3_23">3.23. FIFO 'Timestamp FIFO 0' data output register 0</a></h3>
<h3><a name="sect_3_24">3.24. FIFO 'Timestamp FIFO 0' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9123,7 +9537,7 @@ TSF0_R0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[31:24]
TAG_SECONDS[31:24]
</td>
<td >
......@@ -9177,7 +9591,7 @@ TAG_UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[23:16]
TAG_SECONDS[23:16]
</td>
<td >
......@@ -9231,7 +9645,7 @@ TAG_UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[15:8]
TAG_SECONDS[15:8]
</td>
<td >
......@@ -9285,7 +9699,7 @@ TAG_UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[7:0]
TAG_SECONDS[7:0]
</td>
<td >
......@@ -9312,11 +9726,11 @@ TAG_UTC[7:0]
</table>
<ul>
<li><b>
TAG_UTC
</b>[<i>read-only</i>]: UTC time
TAG_SECONDS
</b>[<i>read-only</i>]: seconds time
</ul>
<a name="TSF0_R1"></a>
<h3><a name="sect_3_24">3.24. FIFO 'Timestamp FIFO 0' data output register 1</a></h3>
<h3><a name="sect_3_25">3.25. FIFO 'Timestamp FIFO 0' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9542,7 +9956,7 @@ TSF0_R1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTCH[7:0]
TAG_SECONDSH[7:0]
</td>
<td >
......@@ -9569,11 +9983,11 @@ TAG_UTCH[7:0]
</table>
<ul>
<li><b>
TAG_UTCH
</b>[<i>read-only</i>]: UTC time H
TAG_SECONDSH
</b>[<i>read-only</i>]: seconds time H
</ul>
<a name="TSF0_R2"></a>
<h3><a name="sect_3_25">3.25. FIFO 'Timestamp FIFO 0' data output register 2</a></h3>
<h3><a name="sect_3_26">3.26. FIFO 'Timestamp FIFO 0' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9830,7 +10244,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy
</ul>
<a name="TSF0_CSR"></a>
<h3><a name="sect_3_26">3.26. FIFO 'Timestamp FIFO 0' control/status register</a></h3>
<h3><a name="sect_3_27">3.27. FIFO 'Timestamp FIFO 0' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10096,7 +10510,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 0'
</ul>
<a name="TSF1_R0"></a>
<h3><a name="sect_3_27">3.27. FIFO 'Timestamp FIFO 1' data output register 0</a></h3>
<h3><a name="sect_3_28">3.28. FIFO 'Timestamp FIFO 1' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10160,7 +10574,7 @@ TSF1_R0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[31:24]
TAG_SECONDS[31:24]
</td>
<td >
......@@ -10214,7 +10628,7 @@ TAG_UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[23:16]
TAG_SECONDS[23:16]
</td>
<td >
......@@ -10268,7 +10682,7 @@ TAG_UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[15:8]
TAG_SECONDS[15:8]
</td>
<td >
......@@ -10322,7 +10736,7 @@ TAG_UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[7:0]
TAG_SECONDS[7:0]
</td>
<td >
......@@ -10349,11 +10763,11 @@ TAG_UTC[7:0]
</table>
<ul>
<li><b>
TAG_UTC
</b>[<i>read-only</i>]: UTC time
TAG_SECONDS
</b>[<i>read-only</i>]: seconds time
</ul>
<a name="TSF1_R1"></a>
<h3><a name="sect_3_28">3.28. FIFO 'Timestamp FIFO 1' data output register 1</a></h3>
<h3><a name="sect_3_29">3.29. FIFO 'Timestamp FIFO 1' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10579,7 +10993,7 @@ TSF1_R1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTCH[7:0]
TAG_SECONDSH[7:0]
</td>
<td >
......@@ -10606,11 +11020,11 @@ TAG_UTCH[7:0]
</table>
<ul>
<li><b>
TAG_UTCH
</b>[<i>read-only</i>]: UTC time H
TAG_SECONDSH
</b>[<i>read-only</i>]: seconds time H
</ul>
<a name="TSF1_R2"></a>
<h3><a name="sect_3_29">3.29. FIFO 'Timestamp FIFO 1' data output register 2</a></h3>
<h3><a name="sect_3_30">3.30. FIFO 'Timestamp FIFO 1' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10867,7 +11281,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy
</ul>
<a name="TSF1_CSR"></a>
<h3><a name="sect_3_30">3.30. FIFO 'Timestamp FIFO 1' control/status register</a></h3>
<h3><a name="sect_3_31">3.31. FIFO 'Timestamp FIFO 1' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11133,7 +11547,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 1'
</ul>
<a name="TSF2_R0"></a>
<h3><a name="sect_3_31">3.31. FIFO 'Timestamp FIFO 2' data output register 0</a></h3>
<h3><a name="sect_3_32">3.32. FIFO 'Timestamp FIFO 2' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11197,7 +11611,7 @@ TSF2_R0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[31:24]
TAG_SECONDS[31:24]
</td>
<td >
......@@ -11251,7 +11665,7 @@ TAG_UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[23:16]
TAG_SECONDS[23:16]
</td>
<td >
......@@ -11305,7 +11719,7 @@ TAG_UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[15:8]
TAG_SECONDS[15:8]
</td>
<td >
......@@ -11359,7 +11773,7 @@ TAG_UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[7:0]
TAG_SECONDS[7:0]
</td>
<td >
......@@ -11386,11 +11800,11 @@ TAG_UTC[7:0]
</table>
<ul>
<li><b>
TAG_UTC
</b>[<i>read-only</i>]: UTC time
TAG_SECONDS
</b>[<i>read-only</i>]: seconds time
</ul>
<a name="TSF2_R1"></a>
<h3><a name="sect_3_32">3.32. FIFO 'Timestamp FIFO 2' data output register 1</a></h3>
<h3><a name="sect_3_33">3.33. FIFO 'Timestamp FIFO 2' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11616,7 +12030,7 @@ TSF2_R1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTCH[7:0]
TAG_SECONDSH[7:0]
</td>
<td >
......@@ -11643,11 +12057,11 @@ TAG_UTCH[7:0]
</table>
<ul>
<li><b>
TAG_UTCH
</b>[<i>read-only</i>]: UTC time H
TAG_SECONDSH
</b>[<i>read-only</i>]: seconds time H
</ul>
<a name="TSF2_R2"></a>
<h3><a name="sect_3_33">3.33. FIFO 'Timestamp FIFO 2' data output register 2</a></h3>
<h3><a name="sect_3_34">3.34. FIFO 'Timestamp FIFO 2' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11904,7 +12318,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy
</ul>
<a name="TSF2_CSR"></a>
<h3><a name="sect_3_34">3.34. FIFO 'Timestamp FIFO 2' control/status register</a></h3>
<h3><a name="sect_3_35">3.35. FIFO 'Timestamp FIFO 2' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12170,7 +12584,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 2'
</ul>
<a name="TSF3_R0"></a>
<h3><a name="sect_3_35">3.35. FIFO 'Timestamp FIFO 3' data output register 0</a></h3>
<h3><a name="sect_3_36">3.36. FIFO 'Timestamp FIFO 3' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12234,7 +12648,7 @@ TSF3_R0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[31:24]
TAG_SECONDS[31:24]
</td>
<td >
......@@ -12288,7 +12702,7 @@ TAG_UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[23:16]
TAG_SECONDS[23:16]
</td>
<td >
......@@ -12342,7 +12756,7 @@ TAG_UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[15:8]
TAG_SECONDS[15:8]
</td>
<td >
......@@ -12396,7 +12810,7 @@ TAG_UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[7:0]
TAG_SECONDS[7:0]
</td>
<td >
......@@ -12423,11 +12837,11 @@ TAG_UTC[7:0]
</table>
<ul>
<li><b>
TAG_UTC
</b>[<i>read-only</i>]: UTC time
TAG_SECONDS
</b>[<i>read-only</i>]: seconds time
</ul>
<a name="TSF3_R1"></a>
<h3><a name="sect_3_36">3.36. FIFO 'Timestamp FIFO 3' data output register 1</a></h3>
<h3><a name="sect_3_37">3.37. FIFO 'Timestamp FIFO 3' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12653,7 +13067,7 @@ TSF3_R1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTCH[7:0]
TAG_SECONDSH[7:0]
</td>
<td >
......@@ -12680,11 +13094,11 @@ TAG_UTCH[7:0]
</table>
<ul>
<li><b>
TAG_UTCH
</b>[<i>read-only</i>]: UTC time H
TAG_SECONDSH
</b>[<i>read-only</i>]: seconds time H
</ul>
<a name="TSF3_R2"></a>
<h3><a name="sect_3_37">3.37. FIFO 'Timestamp FIFO 3' data output register 2</a></h3>
<h3><a name="sect_3_38">3.38. FIFO 'Timestamp FIFO 3' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12941,7 +13355,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy
</ul>
<a name="TSF3_CSR"></a>
<h3><a name="sect_3_38">3.38. FIFO 'Timestamp FIFO 3' control/status register</a></h3>
<h3><a name="sect_3_39">3.39. FIFO 'Timestamp FIFO 3' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13207,7 +13621,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 3'
</ul>
<a name="TSF4_R0"></a>
<h3><a name="sect_3_39">3.39. FIFO 'Timestamp FIFO 4' data output register 0</a></h3>
<h3><a name="sect_3_40">3.40. FIFO 'Timestamp FIFO 4' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13271,7 +13685,7 @@ TSF4_R0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[31:24]
TAG_SECONDS[31:24]
</td>
<td >
......@@ -13325,7 +13739,7 @@ TAG_UTC[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[23:16]
TAG_SECONDS[23:16]
</td>
<td >
......@@ -13379,7 +13793,7 @@ TAG_UTC[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[15:8]
TAG_SECONDS[15:8]
</td>
<td >
......@@ -13433,7 +13847,7 @@ TAG_UTC[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTC[7:0]
TAG_SECONDS[7:0]
</td>
<td >
......@@ -13460,11 +13874,11 @@ TAG_UTC[7:0]
</table>
<ul>
<li><b>
TAG_UTC
</b>[<i>read-only</i>]: UTC time
TAG_SECONDS
</b>[<i>read-only</i>]: seconds time
</ul>
<a name="TSF4_R1"></a>
<h3><a name="sect_3_40">3.40. FIFO 'Timestamp FIFO 4' data output register 1</a></h3>
<h3><a name="sect_3_41">3.41. FIFO 'Timestamp FIFO 4' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13690,7 +14104,7 @@ TSF4_R1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TAG_UTCH[7:0]
TAG_SECONDSH[7:0]
</td>
<td >
......@@ -13717,11 +14131,11 @@ TAG_UTCH[7:0]
</table>
<ul>
<li><b>
TAG_UTCH
</b>[<i>read-only</i>]: UTC time H
TAG_SECONDSH
</b>[<i>read-only</i>]: seconds time H
</ul>
<a name="TSF4_R2"></a>
<h3><a name="sect_3_41">3.41. FIFO 'Timestamp FIFO 4' data output register 2</a></h3>
<h3><a name="sect_3_42">3.42. FIFO 'Timestamp FIFO 4' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13978,7 +14392,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy
</ul>
<a name="TSF4_CSR"></a>
<h3><a name="sect_3_42">3.42. FIFO 'Timestamp FIFO 4' control/status register</a></h3>
<h3><a name="sect_3_43">3.43. FIFO 'Timestamp FIFO 4' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......
modules/wrsw_dio/wrsw_dio_wb.vhd
View file @ 5ae31c31
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Sun Mar 18 11:40:55 2012
-- Created : Fri Jun 29 10:14:46 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
......@@ -36,8 +36,8 @@ entity wrsw_dio_wb is
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
......@@ -46,8 +46,8 @@ entity wrsw_dio_wb is
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
......@@ -56,8 +56,8 @@ entity wrsw_dio_wb is
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
......@@ -66,8 +66,8 @@ entity wrsw_dio_wb is
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
......@@ -76,44 +76,54 @@ entity wrsw_dio_wb is
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trig0_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trigh0_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trig1_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trigh1_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trig2_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trigh2_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trig3_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trigh3_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trig4_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trigh4_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation'
dio_trig_ena_ena_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation'
dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO seconds-based trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
......@@ -154,22 +164,32 @@ signal dio_tsf4_in_int : std_logic_vector(67 downto 0);
signal dio_tsf4_out_int : std_logic_vector(67 downto 0);
signal dio_tsf4_rdreq_int : std_logic ;
signal dio_tsf4_rdreq_int_d0 : std_logic ;
signal dio_trig0_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh0_utc_int : std_logic_vector(7 downto 0);
signal dio_trig0_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh0_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig1_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh1_utc_int : std_logic_vector(7 downto 0);
signal dio_trig1_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh1_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig2_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh2_utc_int : std_logic_vector(7 downto 0);
signal dio_trig2_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh2_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig3_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh3_utc_int : std_logic_vector(7 downto 0);
signal dio_trig3_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh3_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh4_utc_int : std_logic_vector(7 downto 0);
signal dio_trig4_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig_ena_ena_int : std_logic_vector(4 downto 0);
signal dio_out_mode_int : std_logic_vector(4 downto 0);
signal dio_latch_time_ch0_dly0 : std_logic ;
signal dio_latch_time_ch0_int : std_logic ;
signal dio_latch_time_ch1_dly0 : std_logic ;
signal dio_latch_time_ch1_int : std_logic ;
signal dio_latch_time_ch2_dly0 : std_logic ;
signal dio_latch_time_ch2_int : std_logic ;
signal dio_latch_time_ch3_dly0 : std_logic ;
signal dio_latch_time_ch3_int : std_logic ;
signal dio_latch_time_ch4_dly0 : std_logic ;
signal dio_latch_time_ch4_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync0 : std_logic ;
......@@ -247,22 +267,27 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dio_trig0_utc_int <= "00000000000000000000000000000000";
dio_trigh0_utc_int <= "00000000";
dio_trig0_seconds_int <= "00000000000000000000000000000000";
dio_trigh0_seconds_int <= "00000000";
dio_cyc0_cyc_int <= "0000000000000000000000000000";
dio_trig1_utc_int <= "00000000000000000000000000000000";
dio_trigh1_utc_int <= "00000000";
dio_trig1_seconds_int <= "00000000000000000000000000000000";
dio_trigh1_seconds_int <= "00000000";
dio_cyc1_cyc_int <= "0000000000000000000000000000";
dio_trig2_utc_int <= "00000000000000000000000000000000";
dio_trigh2_utc_int <= "00000000";
dio_trig2_seconds_int <= "00000000000000000000000000000000";
dio_trigh2_seconds_int <= "00000000";
dio_cyc2_cyc_int <= "0000000000000000000000000000";
dio_trig3_utc_int <= "00000000000000000000000000000000";
dio_trigh3_utc_int <= "00000000";
dio_trig3_seconds_int <= "00000000000000000000000000000000";
dio_trigh3_seconds_int <= "00000000";
dio_cyc3_cyc_int <= "0000000000000000000000000000";
dio_trig4_utc_int <= "00000000000000000000000000000000";
dio_trigh4_utc_int <= "00000000";
dio_trig4_seconds_int <= "00000000000000000000000000000000";
dio_trigh4_seconds_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_trig_ena_ena_int <= "00000";
dio_out_mode_int <= "00000";
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
dio_puls_inmed_pul_inm_0_int <= '0';
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= '0';
......@@ -287,6 +312,11 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -308,16 +338,16 @@ begin
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
dio_trig0_utc_int <= wrdata_reg(31 downto 0);
dio_trig0_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig0_utc_int;
rddata_reg(31 downto 0) <= dio_trig0_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
dio_trigh0_utc_int <= wrdata_reg(7 downto 0);
dio_trigh0_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh0_utc_int;
rddata_reg(7 downto 0) <= dio_trigh0_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -357,16 +387,16 @@ begin
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
dio_trig1_utc_int <= wrdata_reg(31 downto 0);
dio_trig1_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig1_utc_int;
rddata_reg(31 downto 0) <= dio_trig1_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
dio_trigh1_utc_int <= wrdata_reg(7 downto 0);
dio_trigh1_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh1_utc_int;
rddata_reg(7 downto 0) <= dio_trigh1_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -406,16 +436,16 @@ begin
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
dio_trig2_utc_int <= wrdata_reg(31 downto 0);
dio_trig2_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig2_utc_int;
rddata_reg(31 downto 0) <= dio_trig2_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
dio_trigh2_utc_int <= wrdata_reg(7 downto 0);
dio_trigh2_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh2_utc_int;
rddata_reg(7 downto 0) <= dio_trigh2_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -455,16 +485,16 @@ begin
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
dio_trig3_utc_int <= wrdata_reg(31 downto 0);
dio_trig3_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig3_utc_int;
rddata_reg(31 downto 0) <= dio_trig3_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
dio_trigh3_utc_int <= wrdata_reg(7 downto 0);
dio_trigh3_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh3_utc_int;
rddata_reg(7 downto 0) <= dio_trigh3_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -504,16 +534,16 @@ begin
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
dio_trig4_utc_int <= wrdata_reg(31 downto 0);
dio_trig4_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig4_utc_int;
rddata_reg(31 downto 0) <= dio_trig4_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
dio_trigh4_utc_int <= wrdata_reg(7 downto 0);
dio_trigh4_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh4_utc_int;
rddata_reg(7 downto 0) <= dio_trigh4_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -553,9 +583,9 @@ begin
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
dio_trig_ena_ena_int <= wrdata_reg(4 downto 0);
dio_out_mode_int <= wrdata_reg(4 downto 0);
end if;
rddata_reg(4 downto 0) <= dio_trig_ena_ena_int;
rddata_reg(4 downto 0) <= dio_out_mode_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -587,8 +617,22 @@ begin
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
dio_latch_time_ch0_int <= wrdata_reg(0);
dio_latch_time_ch1_int <= wrdata_reg(1);
dio_latch_time_ch2_int <= wrdata_reg(2);
dio_latch_time_ch3_int <= wrdata_reg(3);
dio_latch_time_ch4_int <= wrdata_reg(4);
end if;
rddata_reg(4 downto 0) <= dio_trig_ena_rdy_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -616,9 +660,42 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= dio_trig_rdy_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
dio_puls_inmed_pul_inm_0_int <= wrdata_reg(0);
dio_puls_inmed_pul_inm_0_int_delay <= wrdata_reg(0);
......@@ -1227,8 +1304,8 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO 0
dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_utc_i;
dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_utch_i;
dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_seconds_i;
dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_secondsh_i;
dio_tsf0_in_int(67 downto 40) <= dio_tsf0_tag_cycles_i;
dio_tsf0_rst_n <= rst_n_i;
dio_tsf0_INST : wbgen2_fifo_sync
......@@ -1252,8 +1329,8 @@ begin
);
-- extra code for reg/fifo/mem: Timestamp FIFO 1
dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_utc_i;
dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_utch_i;
dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_seconds_i;
dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_secondsh_i;
dio_tsf1_in_int(67 downto 40) <= dio_tsf1_tag_cycles_i;
dio_tsf1_rst_n <= rst_n_i;
dio_tsf1_INST : wbgen2_fifo_sync
......@@ -1277,8 +1354,8 @@ begin
);
-- extra code for reg/fifo/mem: Timestamp FIFO 2
dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_utc_i;
dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_utch_i;
dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_seconds_i;
dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_secondsh_i;
dio_tsf2_in_int(67 downto 40) <= dio_tsf2_tag_cycles_i;
dio_tsf2_rst_n <= rst_n_i;
dio_tsf2_INST : wbgen2_fifo_sync
......@@ -1302,8 +1379,8 @@ begin
);
-- extra code for reg/fifo/mem: Timestamp FIFO 3
dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_utc_i;
dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_utch_i;
dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_seconds_i;
dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_secondsh_i;
dio_tsf3_in_int(67 downto 40) <= dio_tsf3_tag_cycles_i;
dio_tsf3_rst_n <= rst_n_i;
dio_tsf3_INST : wbgen2_fifo_sync
......@@ -1327,8 +1404,8 @@ begin
);
-- extra code for reg/fifo/mem: Timestamp FIFO 4
dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_utc_i;
dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_utch_i;
dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_seconds_i;
dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_secondsh_i;
dio_tsf4_in_int(67 downto 40) <= dio_tsf4_tag_cycles_i;
dio_tsf4_rst_n <= rst_n_i;
dio_tsf4_INST : wbgen2_fifo_sync
......@@ -1351,38 +1428,103 @@ begin
rd_data_o => dio_tsf4_out_int
);
-- utc field
dio_trig0_utc_o <= dio_trig0_utc_int;
-- utc field
dio_trigh0_utc_o <= dio_trigh0_utc_int;
-- seconds field
dio_trig0_seconds_o <= dio_trig0_seconds_int;
-- seconds field
dio_trigh0_seconds_o <= dio_trigh0_seconds_int;
-- cycles field
dio_cyc0_cyc_o <= dio_cyc0_cyc_int;
-- utc field
dio_trig1_utc_o <= dio_trig1_utc_int;
-- utc field
dio_trigh1_utc_o <= dio_trigh1_utc_int;
-- seconds field
dio_trig1_seconds_o <= dio_trig1_seconds_int;
-- seconds field
dio_trigh1_seconds_o <= dio_trigh1_seconds_int;
-- cycles field
dio_cyc1_cyc_o <= dio_cyc1_cyc_int;
-- utc field
dio_trig2_utc_o <= dio_trig2_utc_int;
-- utc field
dio_trigh2_utc_o <= dio_trigh2_utc_int;
-- seconds field
dio_trig2_seconds_o <= dio_trig2_seconds_int;
-- seconds field
dio_trigh2_seconds_o <= dio_trigh2_seconds_int;
-- cycles field
dio_cyc2_cyc_o <= dio_cyc2_cyc_int;
-- utc field
dio_trig3_utc_o <= dio_trig3_utc_int;
-- utc field
dio_trigh3_utc_o <= dio_trigh3_utc_int;
-- seconds field
dio_trig3_seconds_o <= dio_trig3_seconds_int;
-- seconds field
dio_trigh3_seconds_o <= dio_trigh3_seconds_int;
-- cycles field
dio_cyc3_cyc_o <= dio_cyc3_cyc_int;
-- utc field
dio_trig4_utc_o <= dio_trig4_utc_int;
-- utc field
dio_trigh4_utc_o <= dio_trigh4_utc_int;
-- seconds field
dio_trig4_seconds_o <= dio_trig4_seconds_int;
-- seconds field
dio_trigh4_seconds_o <= dio_trigh4_seconds_int;
-- cycles field
dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- trig_enable field
dio_trig_ena_ena_o <= dio_trig_ena_ena_int;
-- outmode
dio_out_mode_o <= dio_out_mode_int;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch0_dly0 <= '0';
dio_latch_time_ch0_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch0_dly0 <= dio_latch_time_ch0_int;
dio_latch_time_ch0_o <= dio_latch_time_ch0_int and (not dio_latch_time_ch0_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch1_dly0 <= '0';
dio_latch_time_ch1_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch1_dly0 <= dio_latch_time_ch1_int;
dio_latch_time_ch1_o <= dio_latch_time_ch1_int and (not dio_latch_time_ch1_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch2_dly0 <= '0';
dio_latch_time_ch2_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch2_dly0 <= dio_latch_time_ch2_int;
dio_latch_time_ch2_o <= dio_latch_time_ch2_int and (not dio_latch_time_ch2_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch3_dly0 <= '0';
dio_latch_time_ch3_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch3_dly0 <= dio_latch_time_ch3_int;
dio_latch_time_ch3_o <= dio_latch_time_ch3_int and (not dio_latch_time_ch3_dly0);
end if;
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch4_dly0 <= '0';
dio_latch_time_ch4_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch4_dly0 <= dio_latch_time_ch4_int;
dio_latch_time_ch4_o <= dio_latch_time_ch4_int and (not dio_latch_time_ch4_dly0);
end if;
end process;
-- trig_rdy field
-- pulse_gen_now_0
process (clk_asyn_i, rst_n_i)
......
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