Commit 63766cc4 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Miguel Jimenez Lopez

update components

parent 45736984
......@@ -116,62 +116,62 @@ package wrnic_sdb_pkg is
-- The definition need to be unique and be included into wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_onewire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20120305",
name => "WR-1Wire-master ")));
-- constant c_xwb_onewire_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"779c5443",
-- version => x"00000001",
-- date => x"20120305",
-- name => "WR-1Wire-master ")));
-------------------------------------------------------------------------------
-- WB I2C MASTER --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"123c5443",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WB-I2C-Master ")));
-- constant c_xwb_i2c_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"123c5443",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-I2C-Master ")));
-------------------------------------------------------------------------------
-- WB GPIO --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant c_xwb_gpio_port_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"441c5143",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WB-GPIO-Port ")));
-- constant c_xwb_gpio_port_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"441c5143",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-GPIO-Port ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
......
......@@ -157,17 +157,17 @@ architecture rtl of xwrsw_dio is
-- 1: time given on tm_seconds_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0);
tm_tai_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
tag_utc_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_seconds_o and tag_cycles_o
tag_valid_p1_o : out std_logic
tag_valid_o : out std_logic
);
end component;
......@@ -456,12 +456,12 @@ begin
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_tai_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tag_utc_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_p1_o => tag_valid_p1(i));
tag_tai_o => tag_seconds(i),
tag_cycles_o => tag_cycles(i),
tag_valid_o => tag_valid_p1(i));
end generate gen_pulse_modules;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment