Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC DIO 5ch TTL a
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
6
Issues
6
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC DIO 5ch TTL a
Commits
63766cc4
Commit
63766cc4
authored
Apr 03, 2013
by
Grzegorz Daniluk
Committed by
Miguel Jimenez Lopez
Apr 03, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
update components
parent
45736984
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
53 additions
and
53 deletions
+53
-53
wrnic_sdb_pkg.vhd
modules/wrsw_dio/wrnic_sdb_pkg.vhd
+45
-45
xwrsw_dio.vhd
modules/wrsw_dio/xwrsw_dio.vhd
+8
-8
No files found.
modules/wrsw_dio/wrnic_sdb_pkg.vhd
View file @
63766cc4
...
...
@@ -116,62 +116,62 @@ package wrnic_sdb_pkg is
-- The definition need to be unique and be included into wishbone_pkg
-------------------------------------------------------------------------------
constant
c_xwb_onewire_master_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"779c5443"
,
version
=>
x"00000001"
,
date
=>
x"20120305"
,
name
=>
"WR-1Wire-master "
)));
--
constant c_xwb_onewire_master_sdb : t_sdb_device := (
--
abi_class => x"0000", -- undocumented device
--
abi_ver_major => x"01",
--
abi_ver_minor => x"01",
--
wbd_endian => c_sdb_endian_big,
--
wbd_width => x"7", -- 8/16/32-bit port granularity
--
sdb_component => (
--
addr_first => x"0000000000000000",
--
addr_last => x"00000000000000ff",
--
product => (
--
vendor_id => x"000000000000CE42", -- CERN
--
device_id => x"779c5443",
--
version => x"00000001",
--
date => x"20120305",
--
name => "WR-1Wire-master ")));
-------------------------------------------------------------------------------
-- WB I2C MASTER --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant
c_xwb_i2c_master_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"123c5443"
,
version
=>
x"00000001"
,
date
=>
x"20000101"
,
-- UNKNOWN
name
=>
"WB-I2C-Master "
)));
--
constant c_xwb_i2c_master_sdb : t_sdb_device := (
--
abi_class => x"0000", -- undocumented device
--
abi_ver_major => x"01",
--
abi_ver_minor => x"01",
--
wbd_endian => c_sdb_endian_big,
--
wbd_width => x"7", -- 8/16/32-bit port granularity
--
sdb_component => (
--
addr_first => x"0000000000000000",
--
addr_last => x"00000000000000ff",
--
product => (
--
vendor_id => x"000000000000CE42", -- CERN
--
device_id => x"123c5443",
--
version => x"00000001",
--
date => x"20000101", -- UNKNOWN
--
name => "WB-I2C-Master ")));
-------------------------------------------------------------------------------
-- WB GPIO --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
constant
c_xwb_gpio_port_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"441c5143"
,
version
=>
x"00000001"
,
date
=>
x"20000101"
,
-- UNKNOWN
name
=>
"WB-GPIO-Port "
)));
--
constant c_xwb_gpio_port_sdb : t_sdb_device := (
--
abi_class => x"0000", -- undocumented device
--
abi_ver_major => x"01",
--
abi_ver_minor => x"01",
--
wbd_endian => c_sdb_endian_big,
--
wbd_width => x"7", -- 8/16/32-bit port granularity
--
sdb_component => (
--
addr_first => x"0000000000000000",
--
addr_last => x"00000000000000ff",
--
product => (
--
vendor_id => x"000000000000CE42", -- CERN
--
device_id => x"441c5143",
--
version => x"00000001",
--
date => x"20000101", -- UNKNOWN
--
name => "WB-GPIO-Port ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
...
...
modules/wrsw_dio/xwrsw_dio.vhd
View file @
63766cc4
...
...
@@ -157,17 +157,17 @@ architecture rtl of xwrsw_dio is
-- 1: time given on tm_seconds_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i
:
in
std_logic
;
-- number of seconds
tm_
utc
_i
:
in
std_logic_vector
(
39
downto
0
);
tm_
tai
_i
:
in
std_logic_vector
(
39
downto
0
);
-- number of clk_ref_i cycles
tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
tag_
utc_o
:
out
std_logic_vector
(
39
downto
0
);
tag_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tag_
tai_o
:
out
std_logic_vector
(
39
downto
0
);
tag_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- single-cycle pulse: strobe tag on tag_seconds_o and tag_cycles_o
tag_valid_
p1_o
:
out
std_logic
tag_valid_
o
:
out
std_logic
);
end
component
;
...
...
@@ -456,12 +456,12 @@ begin
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i
=>
tm_time_valid_i
,
tm_
utc
_i
=>
tm_seconds_i
,
tm_
tai
_i
=>
tm_seconds_i
,
tm_cycles_i
=>
tm_cycles_i
,
tag_
utc_o
=>
tag_seconds
(
i
),
tag_cycles_o
=>
tag_cycles
(
i
),
tag_valid_
p1_
o
=>
tag_valid_p1
(
i
));
tag_
tai_o
=>
tag_seconds
(
i
),
tag_cycles_o
=>
tag_cycles
(
i
),
tag_valid_o
=>
tag_valid_p1
(
i
));
end
generate
gen_pulse_modules
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment