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FMC DIO 5ch TTL a
Commit 65134b0d authored by Rafael Rodriguez's avatar Rafael Rodriguez Committed by Miguel Jimenez Lopez
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added functionality: to generate pulses immediately

parent b19d8b3e
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modules/wrsw_dio/wrsw_dio.vhd
View file @ 65134b0d
...@@ -25,7 +25,6 @@ ...@@ -25,7 +25,6 @@
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb -- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W. -- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
library ieee; library ieee;
...@@ -34,7 +33,7 @@ use ieee.numeric_std.all; ...@@ -34,7 +33,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
--use work._pkg.all;
entity wrsw_dio is entity wrsw_dio is
generic ( generic (
...@@ -78,7 +77,9 @@ entity wrsw_dio is ...@@ -78,7 +77,9 @@ entity wrsw_dio is
architecture rtl of wrsw_dio is architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate UTC time) -- Component only for debugging (in order to generate UTC time)
-------------------------------------------------------------------------------
component dummy_time is component dummy_time is
port( port(
clk_sys : in std_logic; clk_sys : in std_logic;
...@@ -86,7 +87,12 @@ architecture rtl of wrsw_dio is ...@@ -86,7 +87,12 @@ architecture rtl of wrsw_dio is
tm_utc : out std_logic_vector(39 downto 0); tm_utc : out std_logic_vector(39 downto 0);
tm_cycles : out std_logic_vector(27 downto 0)); tm_cycles : out std_logic_vector(27 downto 0));
end component; end component;
-------------------------------------------------------------------------------
-- PULSE GENERATOR which produces a 1-tick-long pulse in its
-- output when the UTC time passed to it through a vector equals a
-- pre-programmed UTC time.
-------------------------------------------------------------------------------
component pulse_gen is component pulse_gen is
generic ( generic (
g_ref_clk_rate : integer := 125000000 g_ref_clk_rate : integer := 125000000
...@@ -95,7 +101,7 @@ architecture rtl of wrsw_dio is ...@@ -95,7 +101,7 @@ architecture rtl of wrsw_dio is
clk_ref_i : in std_logic; -- timing reference clock clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset rst_n_i : in std_logic; -- system reset
pulse_o : out std_logic; -- pulse output pulse_o : out std_logic; -- pulse output
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain -- Timing input (from WRPC), clk_ref_i domain
...@@ -120,7 +126,11 @@ architecture rtl of wrsw_dio is ...@@ -120,7 +126,11 @@ architecture rtl of wrsw_dio is
trig_valid_p1_i : in std_logic trig_valid_p1_i : in std_logic
); );
end component; end component;
-------------------------------------------------------------------------------
-- PULSE STAMPER which associates a time-tag with an asyncrhonous
-- input pulse.
-------------------------------------------------------------------------------
component pulse_stamper is component pulse_stamper is
generic ( generic (
-- reference clock frequency -- reference clock frequency
...@@ -153,109 +163,117 @@ architecture rtl of wrsw_dio is ...@@ -153,109 +163,117 @@ architecture rtl of wrsw_dio is
); );
end component; end component;
component wrsw_dio_wb is
port (
component wrsw_dio_wb is
port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0); wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
wb_int_o : out std_logic; wb_int_o : out std_logic;
-- FIFO write request clk_asyn_i : in std_logic;
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic; dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
dio_tsf0_wr_full_o : out std_logic; dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag -- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic; dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_utc_i : in std_logic_vector(31 downto 0); dio_tsf0_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_utch_i : in std_logic_vector(7 downto 0); dio_tsf0_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0); dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic; irq_nempty_0_i : in std_logic;
-- FIFO write request -- FIFO write request
dio_tsf1_wr_req_i : in std_logic; dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
dio_tsf1_wr_full_o : out std_logic; dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag -- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic; dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_utc_i : in std_logic_vector(31 downto 0); dio_tsf1_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_utch_i : in std_logic_vector(7 downto 0); dio_tsf1_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0); dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic; irq_nempty_1_i : in std_logic;
-- FIFO write request -- FIFO write request
dio_tsf2_wr_req_i : in std_logic; dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
dio_tsf2_wr_full_o : out std_logic; dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag -- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic; dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_utc_i : in std_logic_vector(31 downto 0); dio_tsf2_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_utch_i : in std_logic_vector(7 downto 0); dio_tsf2_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0); dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic; irq_nempty_2_i : in std_logic;
-- FIFO write request -- FIFO write request
dio_tsf3_wr_req_i : in std_logic; dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
dio_tsf3_wr_full_o : out std_logic; dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag -- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic; dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_utc_i : in std_logic_vector(31 downto 0); dio_tsf3_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_utch_i : in std_logic_vector(7 downto 0); dio_tsf3_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0); dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic; irq_nempty_3_i : in std_logic;
-- FIFO write request -- FIFO write request
dio_tsf4_wr_req_i : in std_logic; dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
dio_tsf4_wr_full_o : out std_logic; dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag -- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic; dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_utc_i : in std_logic_vector(31 downto 0); dio_tsf4_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_utch_i : in std_logic_vector(7 downto 0); dio_tsf4_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0); dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic; irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trig0_utc_o : out std_logic_vector(31 downto 0); dio_trig0_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trigh0_utc_o : out std_logic_vector(7 downto 0); dio_trigh0_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation' -- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0); dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trig1_utc_o : out std_logic_vector(31 downto 0); dio_trig1_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trigh1_utc_o : out std_logic_vector(7 downto 0); dio_trigh1_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation' -- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0); dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trig2_utc_o : out std_logic_vector(31 downto 0); dio_trig2_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trigh2_utc_o : out std_logic_vector(7 downto 0); dio_trigh2_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation' -- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0); dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trig3_utc_o : out std_logic_vector(31 downto 0); dio_trig3_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trigh3_utc_o : out std_logic_vector(7 downto 0); dio_trigh3_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation' -- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0); dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trig4_utc_o : out std_logic_vector(31 downto 0); dio_trig4_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation' -- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trigh4_utc_o : out std_logic_vector(7 downto 0); dio_trigh4_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation' -- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0); dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation' -- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation'
dio_trig_ena_ena_o : out std_logic_vector(4 downto 0); dio_trig_ena_ena_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation' -- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation'
dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0) dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
); );
end component; end component;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -290,7 +308,6 @@ end component; ...@@ -290,7 +308,6 @@ end component;
signal tag_cycles : t_cycles_array; signal tag_cycles : t_cycles_array;
signal tag_valid_p1 : std_logic_vector (4 downto 0); signal tag_valid_p1 : std_logic_vector (4 downto 0);
-- FIFO signals -- FIFO signals
signal dio_tsf_wr_req : std_logic_vector (4 downto 0); signal dio_tsf_wr_req : std_logic_vector (4 downto 0);
signal dio_tsf_wr_full : std_logic_vector (4 downto 0); signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
...@@ -301,15 +318,18 @@ end component; ...@@ -301,15 +318,18 @@ end component;
-- Fifos no-empty interrupts -- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0); signal irq_nempty : std_logic_vector (4 downto 0);
-- Monostable signals
signal dio_puls_inmed_pul_inm_0 : std_logic;
signal dio_puls_inmed_pul_inm_1 : std_logic;
signal dio_puls_inmed_pul_inm_2 : std_logic;
signal dio_puls_inmed_pul_inm_3 : std_logic;
signal dio_puls_inmed_pul_inm_4 : std_logic;
-- DEBUG SIGNALS FOR USING UTC time values from dummy_time instead WRPC -- DEBUG SIGNALS FOR USING UTC time values from dummy_time instead WRPC
signal tm_utc : std_logic_vector (39 downto 0); signal tm_utc : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0); signal tm_cycles : std_logic_vector (27 downto 0);
-------------------
-- WB Crossbar -- WB Crossbar
-------------------
constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) := constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) :=
(0 => x"00060000", -- ONEWIRE (0 => x"00060000", -- ONEWIRE
1 => x"00060100", -- I2C 1 => x"00060100", -- I2C
...@@ -322,13 +342,14 @@ end component; ...@@ -322,13 +342,14 @@ end component;
2 => x"ffffff00", 2 => x"ffffff00",
3 => x"ffffff00"); 3 => x"ffffff00");
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0); signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0); signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
-- DIO OUT SIGNAL -- DIO SIGNAL
signal dio_out : std_logic_vector (4 downto 0); signal dio_out : std_logic_vector(4 downto 0);
signal dio_puls_inmed : std_logic_vector(4 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- rtl -- rtl
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -336,14 +357,13 @@ begin ...@@ -336,14 +357,13 @@ begin
-- Dummy counter for simulationg WRPC utc time -- Dummy counter for simulationg WRPC utc time
U_dummy: dummy_time U_dummy: dummy_time
port map( port map(
clk_sys => clk_ref_i, clk_sys => clk_ref_i,
rst_n => rst_n_i, rst_n => rst_n_i,
tm_utc => tm_utc, tm_utc => tm_utc,
tm_cycles => tm_cycles tm_cycles => tm_cycles
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- GEN AND STAMPER -- GEN AND STAMPER
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -366,7 +386,7 @@ begin ...@@ -366,7 +386,7 @@ begin
trig_cycles_i => trig_cycles(i), trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i)); trig_valid_p1_i => trig_valid_p1(i));
dio_out_o(i) <= dio_out(i); dio_out_o(i) <= dio_puls_inmed(i) when dio_puls_inmed(i) = '1' else dio_out(i);
U_pulse_stamper : pulse_stamper U_pulse_stamper : pulse_stamper
port map( port map(
...@@ -387,6 +407,13 @@ begin ...@@ -387,6 +407,13 @@ begin
end generate gen_pulse_modules; end generate gen_pulse_modules;
dio_puls_inmed(0) <= dio_puls_inmed_pul_inm_0;
dio_puls_inmed(1) <= dio_puls_inmed_pul_inm_1;
dio_puls_inmed(2) <= dio_puls_inmed_pul_inm_2;
dio_puls_inmed(3) <= dio_puls_inmed_pul_inm_3;
dio_puls_inmed(4) <= dio_puls_inmed_pul_inm_4;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- WB ONEWIRE MASTER -- WB ONEWIRE MASTER
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -504,17 +531,18 @@ begin ...@@ -504,17 +531,18 @@ begin
U_utc_wbslave : wrsw_dio_wb U_utc_wbslave : wrsw_dio_wb
port map( port map(
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
wb_adr_i => cbar_master_out(3).adr(7 downto 2), wb_adr_i => cbar_master_out(3).adr(7 downto 2),
wb_dat_i => cbar_master_out(3).dat, wb_dat_i => cbar_master_out(3).dat,
wb_dat_o => cbar_master_in(3).dat, wb_dat_o => cbar_master_in(3).dat,
wb_cyc_i => cbar_master_out(3).cyc, wb_cyc_i => cbar_master_out(3).cyc,
wb_sel_i => cbar_master_out(3).sel, wb_sel_i => cbar_master_out(3).sel,
wb_stb_i => cbar_master_out(3).stb, wb_stb_i => cbar_master_out(3).stb,
wb_we_i => cbar_master_out(3).we, wb_we_i => cbar_master_out(3).we,
wb_ack_o => cbar_master_in(3).ack, wb_ack_o => cbar_master_in(3).ack,
wb_stall_o => cbar_master_in(3).stall, wb_stall_o => cbar_master_in(3).stall,
wb_int_o => wb_irq_data_fifo_o, --slave_o.int, wb_int_o => wb_irq_data_fifo_o, --slave_o.int,
clk_asyn_i => clk_ref_i,
dio_tsf0_wr_req_i => dio_tsf_wr_req(0), dio_tsf0_wr_req_i => dio_tsf_wr_req(0),
dio_tsf0_wr_full_o => dio_tsf_wr_full(0), dio_tsf0_wr_full_o => dio_tsf_wr_full(0),
...@@ -576,21 +604,23 @@ begin ...@@ -576,21 +604,23 @@ begin
dio_trigh4_utc_o => trig_utc(4)(39 downto 32), dio_trigh4_utc_o => trig_utc(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4), dio_cyc4_cyc_o => trig_cycles(4),
dio_trig_ena_ena_o => trig_valid_p1, dio_trig_ena_ena_o => trig_valid_p1,
dio_trig_ena_rdy_i => trig_ready dio_trig_ena_rdy_i => trig_ready,
dio_puls_inmed_pul_inm_0_o => dio_puls_inmed_pul_inm_0,
dio_puls_inmed_pul_inm_1_o => dio_puls_inmed_pul_inm_1,
dio_puls_inmed_pul_inm_2_o => dio_puls_inmed_pul_inm_2,
dio_puls_inmed_pul_inm_3_o => dio_puls_inmed_pul_inm_3,
dio_puls_inmed_pul_inm_4_o => dio_puls_inmed_pul_inm_4
); );
--interrupt from fifos
--wb_irq_data_fifo_o <= cbar_master_in(3).int;
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
------ signals for debugging ------ signals for debugging
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
TRIG0 <= tag_utc(0)(31 downto 0); -- TRIG0 <= tag_utc(0)(31 downto 0);
-- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0); -- TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
TRIG1(0) <= cbar_master_in(3).int; -- TRIG1(0) <= cbar_master_in(3).int;
TRIG2 <= tm_utc(31 downto 0); -- TRIG2 <= tm_utc(31 downto 0);
TRIG3 <= tm_cycles(21 downto 0) & dio_tsf_wr_empty(4 downto 0) & dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0); TRIG3(2 downto 0) <= dio_in_i(0) & dio_out(0) & dio_puls_inmed(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0); --TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
......
modules/wrsw_dio/wrsw_dio.wb
View file @ 65134b0d
...@@ -535,4 +535,48 @@ peripheral { ...@@ -535,4 +535,48 @@ peripheral {
}; };
-- Pulse generator.
reg {
name = "Pulse generate immediately";
description = "It is used to generate a pulse immediately";
prefix = "puls_inmed";
field {
name = "pulse_gen_now_0";
description = "It generates a pulse";
prefix = "pul_inm_0";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_1";
description = "It generates a pulse";
prefix = "pul_inm_1";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_2";
description = "It generates a pulse";
prefix = "pul_inm_2";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_3";
description = "It generates a pulse";
prefix = "pul_inm_3";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_4";
description = "It generates a pulse";
prefix = "pul_inm_4";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
};
}; };
modules/wrsw_dio/wrsw_dio_wb.htm 100755 → 100644
View file @ 65134b0d
...@@ -51,30 +51,31 @@ ...@@ -51,30 +51,31 @@
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">fmc-dio 4 cycles to trigger a pulse generation</a></span><br/> <span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">fmc-dio 4 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO UTC-based trigger Enable-register for pulse generation</a></span><br/> <span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO UTC-based trigger Enable-register for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">FMC-DIO UTC-based trigger ready informaton for pulse generation</a></span><br/> <span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">FMC-DIO UTC-based trigger ready informaton for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Interrupt disable register</a></span><br/> <span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Pulse generate immediately</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Interrupt enable register</a></span><br/> <span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Interrupt mask register</a></span><br/> <span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Interrupt status register</a></span><br/> <span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">FIFO 'Timestamp FIFO 0' data output register 0</a></span><br/> <span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Interrupt status register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">FIFO 'Timestamp FIFO 0' data output register 1</a></span><br/> <span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">FIFO 'Timestamp FIFO 0' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">FIFO 'Timestamp FIFO 0' data output register 2</a></span><br/> <span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">FIFO 'Timestamp FIFO 0' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">FIFO 'Timestamp FIFO 0' control/status register</a></span><br/> <span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">FIFO 'Timestamp FIFO 0' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">FIFO 'Timestamp FIFO 1' data output register 0</a></span><br/> <span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">FIFO 'Timestamp FIFO 0' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">FIFO 'Timestamp FIFO 1' data output register 1</a></span><br/> <span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">FIFO 'Timestamp FIFO 1' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">FIFO 'Timestamp FIFO 1' data output register 2</a></span><br/> <span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">FIFO 'Timestamp FIFO 1' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">FIFO 'Timestamp FIFO 1' control/status register</a></span><br/> <span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">FIFO 'Timestamp FIFO 1' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">FIFO 'Timestamp FIFO 2' data output register 0</a></span><br/> <span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">FIFO 'Timestamp FIFO 1' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">FIFO 'Timestamp FIFO 2' data output register 1</a></span><br/> <span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">FIFO 'Timestamp FIFO 2' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">FIFO 'Timestamp FIFO 2' data output register 2</a></span><br/> <span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">FIFO 'Timestamp FIFO 2' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">FIFO 'Timestamp FIFO 2' control/status register</a></span><br/> <span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">FIFO 'Timestamp FIFO 2' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">FIFO 'Timestamp FIFO 3' data output register 0</a></span><br/> <span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">FIFO 'Timestamp FIFO 2' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">FIFO 'Timestamp FIFO 3' data output register 1</a></span><br/> <span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">FIFO 'Timestamp FIFO 3' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">FIFO 'Timestamp FIFO 3' data output register 2</a></span><br/> <span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">FIFO 'Timestamp FIFO 3' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">FIFO 'Timestamp FIFO 3' control/status register</a></span><br/> <span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">FIFO 'Timestamp FIFO 3' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">FIFO 'Timestamp FIFO 4' data output register 0</a></span><br/> <span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">FIFO 'Timestamp FIFO 3' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">FIFO 'Timestamp FIFO 4' data output register 1</a></span><br/> <span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">FIFO 'Timestamp FIFO 4' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">FIFO 'Timestamp FIFO 4' data output register 2</a></span><br/> <span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">FIFO 'Timestamp FIFO 4' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">FIFO 'Timestamp FIFO 4' control/status register</a></span><br/> <span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">FIFO 'Timestamp FIFO 4' data output register 2</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">FIFO 'Timestamp FIFO 4' control/status register</a></span><br/>
<span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/> <span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/>
<span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">dio fifo not-empty 0</a></span><br/> <span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">dio fifo not-empty 0</a></span><br/>
<span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">dio fifo not-empty 1</a></span><br/> <span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">dio fifo not-empty 1</a></span><br/>
...@@ -391,6 +392,23 @@ TRIG_ENA ...@@ -391,6 +392,23 @@ TRIG_ENA
</tr> </tr>
<tr class="tr_even"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x11
</td>
<td >
REG
</td>
<td >
<A href="#PULS_INMED">Pulse generate immediately</a>
</td>
<td class="td_code">
dio_puls_inmed
</td>
<td class="td_code">
PULS_INMED
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x18 0x18
</td> </td>
<td > <td >
...@@ -406,7 +424,7 @@ dio_eic_idr ...@@ -406,7 +424,7 @@ dio_eic_idr
EIC_IDR EIC_IDR
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x19 0x19
</td> </td>
...@@ -423,7 +441,7 @@ dio_eic_ier ...@@ -423,7 +441,7 @@ dio_eic_ier
EIC_IER EIC_IER
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x1a 0x1a
</td> </td>
...@@ -440,7 +458,7 @@ dio_eic_imr ...@@ -440,7 +458,7 @@ dio_eic_imr
EIC_IMR EIC_IMR
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x1b 0x1b
</td> </td>
...@@ -457,7 +475,7 @@ dio_eic_isr ...@@ -457,7 +475,7 @@ dio_eic_isr
EIC_ISR EIC_ISR
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x1c 0x1c
</td> </td>
...@@ -474,7 +492,7 @@ dio_tsf0_r0 ...@@ -474,7 +492,7 @@ dio_tsf0_r0
TSF0_R0 TSF0_R0
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x1d 0x1d
</td> </td>
...@@ -491,7 +509,7 @@ dio_tsf0_r1 ...@@ -491,7 +509,7 @@ dio_tsf0_r1
TSF0_R1 TSF0_R1
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x1e 0x1e
</td> </td>
...@@ -508,7 +526,7 @@ dio_tsf0_r2 ...@@ -508,7 +526,7 @@ dio_tsf0_r2
TSF0_R2 TSF0_R2
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x1f 0x1f
</td> </td>
...@@ -525,7 +543,7 @@ dio_tsf0_csr ...@@ -525,7 +543,7 @@ dio_tsf0_csr
TSF0_CSR TSF0_CSR
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x20 0x20
</td> </td>
...@@ -542,7 +560,7 @@ dio_tsf1_r0 ...@@ -542,7 +560,7 @@ dio_tsf1_r0
TSF1_R0 TSF1_R0
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x21 0x21
</td> </td>
...@@ -559,7 +577,7 @@ dio_tsf1_r1 ...@@ -559,7 +577,7 @@ dio_tsf1_r1
TSF1_R1 TSF1_R1
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x22 0x22
</td> </td>
...@@ -576,7 +594,7 @@ dio_tsf1_r2 ...@@ -576,7 +594,7 @@ dio_tsf1_r2
TSF1_R2 TSF1_R2
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x23 0x23
</td> </td>
...@@ -593,7 +611,7 @@ dio_tsf1_csr ...@@ -593,7 +611,7 @@ dio_tsf1_csr
TSF1_CSR TSF1_CSR
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x24 0x24
</td> </td>
...@@ -610,7 +628,7 @@ dio_tsf2_r0 ...@@ -610,7 +628,7 @@ dio_tsf2_r0
TSF2_R0 TSF2_R0
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x25 0x25
</td> </td>
...@@ -627,7 +645,7 @@ dio_tsf2_r1 ...@@ -627,7 +645,7 @@ dio_tsf2_r1
TSF2_R1 TSF2_R1
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x26 0x26
</td> </td>
...@@ -644,7 +662,7 @@ dio_tsf2_r2 ...@@ -644,7 +662,7 @@ dio_tsf2_r2
TSF2_R2 TSF2_R2
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x27 0x27
</td> </td>
...@@ -661,7 +679,7 @@ dio_tsf2_csr ...@@ -661,7 +679,7 @@ dio_tsf2_csr
TSF2_CSR TSF2_CSR
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x28 0x28
</td> </td>
...@@ -678,7 +696,7 @@ dio_tsf3_r0 ...@@ -678,7 +696,7 @@ dio_tsf3_r0
TSF3_R0 TSF3_R0
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x29 0x29
</td> </td>
...@@ -695,7 +713,7 @@ dio_tsf3_r1 ...@@ -695,7 +713,7 @@ dio_tsf3_r1
TSF3_R1 TSF3_R1
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x2a 0x2a
</td> </td>
...@@ -712,7 +730,7 @@ dio_tsf3_r2 ...@@ -712,7 +730,7 @@ dio_tsf3_r2
TSF3_R2 TSF3_R2
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x2b 0x2b
</td> </td>
...@@ -729,7 +747,7 @@ dio_tsf3_csr ...@@ -729,7 +747,7 @@ dio_tsf3_csr
TSF3_CSR TSF3_CSR
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x2c 0x2c
</td> </td>
...@@ -746,7 +764,7 @@ dio_tsf4_r0 ...@@ -746,7 +764,7 @@ dio_tsf4_r0
TSF4_R0 TSF4_R0
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x2d 0x2d
</td> </td>
...@@ -763,7 +781,7 @@ dio_tsf4_r1 ...@@ -763,7 +781,7 @@ dio_tsf4_r1
TSF4_R1 TSF4_R1
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_odd">
<td class="td_code"> <td class="td_code">
0x2e 0x2e
</td> </td>
...@@ -780,7 +798,7 @@ dio_tsf4_r2 ...@@ -780,7 +798,7 @@ dio_tsf4_r2
TSF4_R2 TSF4_R2
</td> </td>
</tr> </tr>
<tr class="tr_odd"> <tr class="tr_even">
<td class="td_code"> <td class="td_code">
0x2f 0x2f
</td> </td>
...@@ -823,7 +841,7 @@ rst_n_i ...@@ -823,7 +841,7 @@ rst_n_i
&rarr; &rarr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_clk_i clk_sys_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -840,7 +858,7 @@ dio_tsf0_wr_req_i ...@@ -840,7 +858,7 @@ dio_tsf0_wr_req_i
&rArr; &rArr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_addr_i[5:0] wb_adr_i[5:0]
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -857,7 +875,7 @@ dio_tsf0_wr_full_o ...@@ -857,7 +875,7 @@ dio_tsf0_wr_full_o
&rArr; &rArr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_data_i[31:0] wb_dat_i[31:0]
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -874,7 +892,7 @@ dio_tsf0_wr_empty_o ...@@ -874,7 +892,7 @@ dio_tsf0_wr_empty_o
&lArr; &lArr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_data_o[31:0] wb_dat_o[31:0]
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -976,7 +994,7 @@ irq_nempty_0_i ...@@ -976,7 +994,7 @@ irq_nempty_0_i
&larr; &larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_irq_o wb_stall_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -990,10 +1008,10 @@ wb_irq_o ...@@ -990,10 +1008,10 @@ wb_irq_o
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_int_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -2612,6 +2630,125 @@ dio_trig_ena_rdy_i[4:0] ...@@ -2612,6 +2630,125 @@ dio_trig_ena_rdy_i[4:0]
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Pulse generate immediately:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_puls_inmed_pul_inm_0_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_puls_inmed_pul_inm_1_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_puls_inmed_pul_inm_2_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_puls_inmed_pul_inm_3_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_puls_inmed_pul_inm_4_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
<b>FIFO 'Timestamp FIFO 0' data output register 0:</b> <b>FIFO 'Timestamp FIFO 0' data output register 0:</b>
...@@ -7536,8 +7673,285 @@ RDY ...@@ -7536,8 +7673,285 @@ RDY
</b>[<i>read-only</i>]: trig_rdy field </b>[<i>read-only</i>]: trig_rdy field
<br>TBD <br>TBD
</ul> </ul>
<a name="PULS_INMED"></a>
<h3><a name="sect_3_18">3.18. Pulse generate immediately</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dio_puls_inmed
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x11
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
PULS_INMED
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x44
</td>
</tr>
</table>
<p>
It is used to generate a pulse immediately
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PUL_INM_4
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PUL_INM_3
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PUL_INM_2
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PUL_INM_1
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PUL_INM_0
</td>
</tr>
</table>
<ul>
<li><b>
PUL_INM_0
</b>[<i>write-only</i>]: pulse_gen_now_0
<br>It generates a pulse
<li><b>
PUL_INM_1
</b>[<i>write-only</i>]: pulse_gen_now_1
<br>It generates a pulse
<li><b>
PUL_INM_2
</b>[<i>write-only</i>]: pulse_gen_now_2
<br>It generates a pulse
<li><b>
PUL_INM_3
</b>[<i>write-only</i>]: pulse_gen_now_3
<br>It generates a pulse
<li><b>
PUL_INM_4
</b>[<i>write-only</i>]: pulse_gen_now_4
<br>It generates a pulse
</ul>
<a name="EIC_IDR"></a> <a name="EIC_IDR"></a>
<h3><a name="sect_3_18">3.18. Interrupt disable register</a></h3> <h3><a name="sect_3_19">3.19. Interrupt disable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -7814,7 +8228,7 @@ NEMPTY_4 ...@@ -7814,7 +8228,7 @@ NEMPTY_4
<br>write 1: disable interrupt 'dio fifo not-empty 4'<br>write 0: no effect <br>write 1: disable interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul> </ul>
<a name="EIC_IER"></a> <a name="EIC_IER"></a>
<h3><a name="sect_3_19">3.19. Interrupt enable register</a></h3> <h3><a name="sect_3_20">3.20. Interrupt enable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -8091,7 +8505,7 @@ NEMPTY_4 ...@@ -8091,7 +8505,7 @@ NEMPTY_4
<br>write 1: enable interrupt 'dio fifo not-empty 4'<br>write 0: no effect <br>write 1: enable interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul> </ul>
<a name="EIC_IMR"></a> <a name="EIC_IMR"></a>
<h3><a name="sect_3_20">3.20. Interrupt mask register</a></h3> <h3><a name="sect_3_21">3.21. Interrupt mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -8368,7 +8782,7 @@ NEMPTY_4 ...@@ -8368,7 +8782,7 @@ NEMPTY_4
<br>read 1: interrupt 'dio fifo not-empty 4' is enabled<br>read 0: interrupt 'dio fifo not-empty 4' is disabled <br>read 1: interrupt 'dio fifo not-empty 4' is enabled<br>read 0: interrupt 'dio fifo not-empty 4' is disabled
</ul> </ul>
<a name="EIC_ISR"></a> <a name="EIC_ISR"></a>
<h3><a name="sect_3_21">3.21. Interrupt status register</a></h3> <h3><a name="sect_3_22">3.22. Interrupt status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -8645,7 +9059,7 @@ NEMPTY_4 ...@@ -8645,7 +9059,7 @@ NEMPTY_4
<br>read 1: interrupt 'dio fifo not-empty 4' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'dio fifo not-empty 4'<br>write 0: no effect <br>read 1: interrupt 'dio fifo not-empty 4' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'dio fifo not-empty 4'<br>write 0: no effect
</ul> </ul>
<a name="TSF0_R0"></a> <a name="TSF0_R0"></a>
<h3><a name="sect_3_22">3.22. FIFO 'Timestamp FIFO 0' data output register 0</a></h3> <h3><a name="sect_3_23">3.23. FIFO 'Timestamp FIFO 0' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -8902,7 +9316,7 @@ TAG_UTC ...@@ -8902,7 +9316,7 @@ TAG_UTC
</b>[<i>read-only</i>]: UTC time </b>[<i>read-only</i>]: UTC time
</ul> </ul>
<a name="TSF0_R1"></a> <a name="TSF0_R1"></a>
<h3><a name="sect_3_23">3.23. FIFO 'Timestamp FIFO 0' data output register 1</a></h3> <h3><a name="sect_3_24">3.24. FIFO 'Timestamp FIFO 0' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -9159,7 +9573,7 @@ TAG_UTCH ...@@ -9159,7 +9573,7 @@ TAG_UTCH
</b>[<i>read-only</i>]: UTC time H </b>[<i>read-only</i>]: UTC time H
</ul> </ul>
<a name="TSF0_R2"></a> <a name="TSF0_R2"></a>
<h3><a name="sect_3_24">3.24. FIFO 'Timestamp FIFO 0' data output register 2</a></h3> <h3><a name="sect_3_25">3.25. FIFO 'Timestamp FIFO 0' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -9416,7 +9830,7 @@ TAG_CYCLES ...@@ -9416,7 +9830,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy </b>[<i>read-only</i>]: Sub-second accuracy
</ul> </ul>
<a name="TSF0_CSR"></a> <a name="TSF0_CSR"></a>
<h3><a name="sect_3_25">3.25. FIFO 'Timestamp FIFO 0' control/status register</a></h3> <h3><a name="sect_3_26">3.26. FIFO 'Timestamp FIFO 0' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -9682,7 +10096,7 @@ USEDW ...@@ -9682,7 +10096,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 0' <br>Number of data records currently being stored in FIFO 'Timestamp FIFO 0'
</ul> </ul>
<a name="TSF1_R0"></a> <a name="TSF1_R0"></a>
<h3><a name="sect_3_26">3.26. FIFO 'Timestamp FIFO 1' data output register 0</a></h3> <h3><a name="sect_3_27">3.27. FIFO 'Timestamp FIFO 1' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -9939,7 +10353,7 @@ TAG_UTC ...@@ -9939,7 +10353,7 @@ TAG_UTC
</b>[<i>read-only</i>]: UTC time </b>[<i>read-only</i>]: UTC time
</ul> </ul>
<a name="TSF1_R1"></a> <a name="TSF1_R1"></a>
<h3><a name="sect_3_27">3.27. FIFO 'Timestamp FIFO 1' data output register 1</a></h3> <h3><a name="sect_3_28">3.28. FIFO 'Timestamp FIFO 1' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -10196,7 +10610,7 @@ TAG_UTCH ...@@ -10196,7 +10610,7 @@ TAG_UTCH
</b>[<i>read-only</i>]: UTC time H </b>[<i>read-only</i>]: UTC time H
</ul> </ul>
<a name="TSF1_R2"></a> <a name="TSF1_R2"></a>
<h3><a name="sect_3_28">3.28. FIFO 'Timestamp FIFO 1' data output register 2</a></h3> <h3><a name="sect_3_29">3.29. FIFO 'Timestamp FIFO 1' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -10453,7 +10867,7 @@ TAG_CYCLES ...@@ -10453,7 +10867,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy </b>[<i>read-only</i>]: Sub-second accuracy
</ul> </ul>
<a name="TSF1_CSR"></a> <a name="TSF1_CSR"></a>
<h3><a name="sect_3_29">3.29. FIFO 'Timestamp FIFO 1' control/status register</a></h3> <h3><a name="sect_3_30">3.30. FIFO 'Timestamp FIFO 1' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -10719,7 +11133,7 @@ USEDW ...@@ -10719,7 +11133,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 1' <br>Number of data records currently being stored in FIFO 'Timestamp FIFO 1'
</ul> </ul>
<a name="TSF2_R0"></a> <a name="TSF2_R0"></a>
<h3><a name="sect_3_30">3.30. FIFO 'Timestamp FIFO 2' data output register 0</a></h3> <h3><a name="sect_3_31">3.31. FIFO 'Timestamp FIFO 2' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -10976,7 +11390,7 @@ TAG_UTC ...@@ -10976,7 +11390,7 @@ TAG_UTC
</b>[<i>read-only</i>]: UTC time </b>[<i>read-only</i>]: UTC time
</ul> </ul>
<a name="TSF2_R1"></a> <a name="TSF2_R1"></a>
<h3><a name="sect_3_31">3.31. FIFO 'Timestamp FIFO 2' data output register 1</a></h3> <h3><a name="sect_3_32">3.32. FIFO 'Timestamp FIFO 2' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -11233,7 +11647,7 @@ TAG_UTCH ...@@ -11233,7 +11647,7 @@ TAG_UTCH
</b>[<i>read-only</i>]: UTC time H </b>[<i>read-only</i>]: UTC time H
</ul> </ul>
<a name="TSF2_R2"></a> <a name="TSF2_R2"></a>
<h3><a name="sect_3_32">3.32. FIFO 'Timestamp FIFO 2' data output register 2</a></h3> <h3><a name="sect_3_33">3.33. FIFO 'Timestamp FIFO 2' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -11490,7 +11904,7 @@ TAG_CYCLES ...@@ -11490,7 +11904,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy </b>[<i>read-only</i>]: Sub-second accuracy
</ul> </ul>
<a name="TSF2_CSR"></a> <a name="TSF2_CSR"></a>
<h3><a name="sect_3_33">3.33. FIFO 'Timestamp FIFO 2' control/status register</a></h3> <h3><a name="sect_3_34">3.34. FIFO 'Timestamp FIFO 2' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -11756,7 +12170,7 @@ USEDW ...@@ -11756,7 +12170,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 2' <br>Number of data records currently being stored in FIFO 'Timestamp FIFO 2'
</ul> </ul>
<a name="TSF3_R0"></a> <a name="TSF3_R0"></a>
<h3><a name="sect_3_34">3.34. FIFO 'Timestamp FIFO 3' data output register 0</a></h3> <h3><a name="sect_3_35">3.35. FIFO 'Timestamp FIFO 3' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -12013,7 +12427,7 @@ TAG_UTC ...@@ -12013,7 +12427,7 @@ TAG_UTC
</b>[<i>read-only</i>]: UTC time </b>[<i>read-only</i>]: UTC time
</ul> </ul>
<a name="TSF3_R1"></a> <a name="TSF3_R1"></a>
<h3><a name="sect_3_35">3.35. FIFO 'Timestamp FIFO 3' data output register 1</a></h3> <h3><a name="sect_3_36">3.36. FIFO 'Timestamp FIFO 3' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -12270,7 +12684,7 @@ TAG_UTCH ...@@ -12270,7 +12684,7 @@ TAG_UTCH
</b>[<i>read-only</i>]: UTC time H </b>[<i>read-only</i>]: UTC time H
</ul> </ul>
<a name="TSF3_R2"></a> <a name="TSF3_R2"></a>
<h3><a name="sect_3_36">3.36. FIFO 'Timestamp FIFO 3' data output register 2</a></h3> <h3><a name="sect_3_37">3.37. FIFO 'Timestamp FIFO 3' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -12527,7 +12941,7 @@ TAG_CYCLES ...@@ -12527,7 +12941,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy </b>[<i>read-only</i>]: Sub-second accuracy
</ul> </ul>
<a name="TSF3_CSR"></a> <a name="TSF3_CSR"></a>
<h3><a name="sect_3_37">3.37. FIFO 'Timestamp FIFO 3' control/status register</a></h3> <h3><a name="sect_3_38">3.38. FIFO 'Timestamp FIFO 3' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -12793,7 +13207,7 @@ USEDW ...@@ -12793,7 +13207,7 @@ USEDW
<br>Number of data records currently being stored in FIFO 'Timestamp FIFO 3' <br>Number of data records currently being stored in FIFO 'Timestamp FIFO 3'
</ul> </ul>
<a name="TSF4_R0"></a> <a name="TSF4_R0"></a>
<h3><a name="sect_3_38">3.38. FIFO 'Timestamp FIFO 4' data output register 0</a></h3> <h3><a name="sect_3_39">3.39. FIFO 'Timestamp FIFO 4' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -13050,7 +13464,7 @@ TAG_UTC ...@@ -13050,7 +13464,7 @@ TAG_UTC
</b>[<i>read-only</i>]: UTC time </b>[<i>read-only</i>]: UTC time
</ul> </ul>
<a name="TSF4_R1"></a> <a name="TSF4_R1"></a>
<h3><a name="sect_3_39">3.39. FIFO 'Timestamp FIFO 4' data output register 1</a></h3> <h3><a name="sect_3_40">3.40. FIFO 'Timestamp FIFO 4' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -13307,7 +13721,7 @@ TAG_UTCH ...@@ -13307,7 +13721,7 @@ TAG_UTCH
</b>[<i>read-only</i>]: UTC time H </b>[<i>read-only</i>]: UTC time H
</ul> </ul>
<a name="TSF4_R2"></a> <a name="TSF4_R2"></a>
<h3><a name="sect_3_40">3.40. FIFO 'Timestamp FIFO 4' data output register 2</a></h3> <h3><a name="sect_3_41">3.41. FIFO 'Timestamp FIFO 4' data output register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
...@@ -13564,7 +13978,7 @@ TAG_CYCLES ...@@ -13564,7 +13978,7 @@ TAG_CYCLES
</b>[<i>read-only</i>]: Sub-second accuracy </b>[<i>read-only</i>]: Sub-second accuracy
</ul> </ul>
<a name="TSF4_CSR"></a> <a name="TSF4_CSR"></a>
<h3><a name="sect_3_41">3.41. FIFO 'Timestamp FIFO 4' control/status register</a></h3> <h3><a name="sect_3_42">3.42. FIFO 'Timestamp FIFO 4' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
......
modules/wrsw_dio/wrsw_dio_wb.vhd 100755 → 100644
View file @ 65134b0d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd -- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb -- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Tue Mar 13 19:59:48 2012 -- Created : Sun Mar 18 11:40:55 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
...@@ -29,6 +29,7 @@ entity wrsw_dio_wb is ...@@ -29,6 +29,7 @@ entity wrsw_dio_wb is
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
wb_int_o : out std_logic; wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request -- FIFO write request
dio_tsf0_wr_req_i : in std_logic; dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag -- FIFO full flag
...@@ -112,7 +113,17 @@ entity wrsw_dio_wb is ...@@ -112,7 +113,17 @@ entity wrsw_dio_wb is
-- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation' -- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation'
dio_trig_ena_ena_o : out std_logic_vector(4 downto 0); dio_trig_ena_ena_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation' -- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation'
dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0) dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_puls_inmed_pul_inm_4_o : out std_logic
); );
end wrsw_dio_wb; end wrsw_dio_wb;
...@@ -159,6 +170,31 @@ signal dio_trig4_utc_int : std_logic_vector(31 downto 0); ...@@ -159,6 +170,31 @@ signal dio_trig4_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh4_utc_int : std_logic_vector(7 downto 0); signal dio_trigh4_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0); signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig_ena_ena_int : std_logic_vector(4 downto 0); signal dio_trig_ena_ena_int : std_logic_vector(4 downto 0);
signal dio_puls_inmed_pul_inm_0_int : std_logic ;
signal dio_puls_inmed_pul_inm_0_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_0_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_1_int : std_logic ;
signal dio_puls_inmed_pul_inm_1_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_1_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_2_int : std_logic ;
signal dio_puls_inmed_pul_inm_2_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_2_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_3_int : std_logic ;
signal dio_puls_inmed_pul_inm_3_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_3_sync2 : std_logic ;
signal dio_puls_inmed_pul_inm_4_int : std_logic ;
signal dio_puls_inmed_pul_inm_4_int_delay : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync0 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync1 : std_logic ;
signal dio_puls_inmed_pul_inm_4_sync2 : std_logic ;
signal eic_idr_int : std_logic_vector(4 downto 0); signal eic_idr_int : std_logic_vector(4 downto 0);
signal eic_idr_write_int : std_logic ; signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0); signal eic_ier_int : std_logic_vector(4 downto 0);
...@@ -227,6 +263,16 @@ begin ...@@ -227,6 +263,16 @@ begin
dio_trigh4_utc_int <= "00000000"; dio_trigh4_utc_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000"; dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_trig_ena_ena_int <= "00000"; dio_trig_ena_ena_int <= "00000";
dio_puls_inmed_pul_inm_0_int <= '0';
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= '0';
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= '0';
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= '0';
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= '0';
dio_puls_inmed_pul_inm_4_int_delay <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
eic_ier_write_int <= '0'; eic_ier_write_int <= '0';
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
...@@ -246,6 +292,16 @@ begin ...@@ -246,6 +292,16 @@ begin
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
dio_puls_inmed_pul_inm_0_int <= dio_puls_inmed_pul_inm_0_int_delay;
dio_puls_inmed_pul_inm_0_int_delay <= '0';
dio_puls_inmed_pul_inm_1_int <= dio_puls_inmed_pul_inm_1_int_delay;
dio_puls_inmed_pul_inm_1_int_delay <= '0';
dio_puls_inmed_pul_inm_2_int <= dio_puls_inmed_pul_inm_2_int_delay;
dio_puls_inmed_pul_inm_2_int_delay <= '0';
dio_puls_inmed_pul_inm_3_int <= dio_puls_inmed_pul_inm_3_int_delay;
dio_puls_inmed_pul_inm_3_int_delay <= '0';
dio_puls_inmed_pul_inm_4_int <= dio_puls_inmed_pul_inm_4_int_delay;
dio_puls_inmed_pul_inm_4_int_delay <= '0';
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
...@@ -562,6 +618,58 @@ begin ...@@ -562,6 +618,58 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
dio_puls_inmed_pul_inm_0_int <= wrdata_reg(0);
dio_puls_inmed_pul_inm_0_int_delay <= wrdata_reg(0);
dio_puls_inmed_pul_inm_1_int <= wrdata_reg(1);
dio_puls_inmed_pul_inm_1_int_delay <= wrdata_reg(1);
dio_puls_inmed_pul_inm_2_int <= wrdata_reg(2);
dio_puls_inmed_pul_inm_2_int_delay <= wrdata_reg(2);
dio_puls_inmed_pul_inm_3_int <= wrdata_reg(3);
dio_puls_inmed_pul_inm_3_int_delay <= wrdata_reg(3);
dio_puls_inmed_pul_inm_4_int <= wrdata_reg(4);
dio_puls_inmed_pul_inm_4_int_delay <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "011000" => when "011000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
eic_idr_write_int <= '1'; eic_idr_write_int <= '1';
...@@ -1276,6 +1384,91 @@ begin ...@@ -1276,6 +1384,91 @@ begin
-- trig_enable field -- trig_enable field
dio_trig_ena_ena_o <= dio_trig_ena_ena_int; dio_trig_ena_ena_o <= dio_trig_ena_ena_int;
-- trig_rdy field -- trig_rdy field
-- pulse_gen_now_0
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_0_o <= '0';
dio_puls_inmed_pul_inm_0_sync0 <= '0';
dio_puls_inmed_pul_inm_0_sync1 <= '0';
dio_puls_inmed_pul_inm_0_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_0_sync0 <= dio_puls_inmed_pul_inm_0_int;
dio_puls_inmed_pul_inm_0_sync1 <= dio_puls_inmed_pul_inm_0_sync0;
dio_puls_inmed_pul_inm_0_sync2 <= dio_puls_inmed_pul_inm_0_sync1;
dio_puls_inmed_pul_inm_0_o <= dio_puls_inmed_pul_inm_0_sync2 and (not dio_puls_inmed_pul_inm_0_sync1);
end if;
end process;
-- pulse_gen_now_1
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_1_o <= '0';
dio_puls_inmed_pul_inm_1_sync0 <= '0';
dio_puls_inmed_pul_inm_1_sync1 <= '0';
dio_puls_inmed_pul_inm_1_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_1_sync0 <= dio_puls_inmed_pul_inm_1_int;
dio_puls_inmed_pul_inm_1_sync1 <= dio_puls_inmed_pul_inm_1_sync0;
dio_puls_inmed_pul_inm_1_sync2 <= dio_puls_inmed_pul_inm_1_sync1;
dio_puls_inmed_pul_inm_1_o <= dio_puls_inmed_pul_inm_1_sync2 and (not dio_puls_inmed_pul_inm_1_sync1);
end if;
end process;
-- pulse_gen_now_2
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_2_o <= '0';
dio_puls_inmed_pul_inm_2_sync0 <= '0';
dio_puls_inmed_pul_inm_2_sync1 <= '0';
dio_puls_inmed_pul_inm_2_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_2_sync0 <= dio_puls_inmed_pul_inm_2_int;
dio_puls_inmed_pul_inm_2_sync1 <= dio_puls_inmed_pul_inm_2_sync0;
dio_puls_inmed_pul_inm_2_sync2 <= dio_puls_inmed_pul_inm_2_sync1;
dio_puls_inmed_pul_inm_2_o <= dio_puls_inmed_pul_inm_2_sync2 and (not dio_puls_inmed_pul_inm_2_sync1);
end if;
end process;
-- pulse_gen_now_3
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_3_o <= '0';
dio_puls_inmed_pul_inm_3_sync0 <= '0';
dio_puls_inmed_pul_inm_3_sync1 <= '0';
dio_puls_inmed_pul_inm_3_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_3_sync0 <= dio_puls_inmed_pul_inm_3_int;
dio_puls_inmed_pul_inm_3_sync1 <= dio_puls_inmed_pul_inm_3_sync0;
dio_puls_inmed_pul_inm_3_sync2 <= dio_puls_inmed_pul_inm_3_sync1;
dio_puls_inmed_pul_inm_3_o <= dio_puls_inmed_pul_inm_3_sync2 and (not dio_puls_inmed_pul_inm_3_sync1);
end if;
end process;
-- pulse_gen_now_4
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_puls_inmed_pul_inm_4_o <= '0';
dio_puls_inmed_pul_inm_4_sync0 <= '0';
dio_puls_inmed_pul_inm_4_sync1 <= '0';
dio_puls_inmed_pul_inm_4_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_puls_inmed_pul_inm_4_sync0 <= dio_puls_inmed_pul_inm_4_int;
dio_puls_inmed_pul_inm_4_sync1 <= dio_puls_inmed_pul_inm_4_sync0;
dio_puls_inmed_pul_inm_4_sync2 <= dio_puls_inmed_pul_inm_4_sync1;
dio_puls_inmed_pul_inm_4_o <= dio_puls_inmed_pul_inm_4_sync2 and (not dio_puls_inmed_pul_inm_4_sync1);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register -- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0); eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register -- extra code for reg/fifo/mem: Interrupt enable register
......
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