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FMC DIO 5ch TTL a
Commits
6f8ac345
Commit
6f8ac345
authored
May 05, 2020
by
Jorge Machado
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Add wr-dio-reg.c file to allow access to both DIO versions
parent
a1da3b7e
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651 deletions
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-651
wr-dio-regs.c
sw/kernel/hw/wr-dio-regs.c
+18
-0
wr-dio-regs.h
sw/kernel/hw/wr-dio-regs.h
+32
-651
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sw/kernel/hw/wr-dio-regs.c
0 → 100644
View file @
6f8ac345
#include "wr-dio-regs.h"
struct
regmap
*
get_regmap
(
unsigned
int
ver
)
{
if
(
ver
==
0
)
return
regmap_v1
;
else
return
regmap_v2
;
}
struct
regmap_common
get_regmap_common
(
unsigned
int
ver
)
{
if
(
ver
==
0
)
return
regmap_common_v1
;
else
return
regmap_common_v2
;
}
\ No newline at end of file
sw/kernel/hw/wr-dio-regs.h
View file @
6f8ac345
/*
Register definitions for slave core: FMC-DIO-5chttla
* File : wr-dio-regs.h
* Author : auto-generated by wbgen2 from wr-dio-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr-dio-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WR_DIO
#define __WBGEN2_REGDEFS_WR_DIO
...
...
@@ -26,346 +14,37 @@
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: fmc-dio 0 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 0 seconds-based trigger for pulse generation */
#define DIO_TRIG0_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TRIG0_SECONDS_SHIFT 0
#define DIO_TRIG0_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TRIG0_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: fmc-dio 0 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 0 seconds-based trigger for pulse generation */
#define DIO_TRIGH0_SECONDS_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TRIGH0_SECONDS_SHIFT 0
#define DIO_TRIGH0_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TRIGH0_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: fmc-dio 0 cycles to trigger a pulse generation */
/* definitions for field: cycles field in reg: fmc-dio 0 cycles to trigger a pulse generation */
#define DIO_CYC0_CYC_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_CYC0_CYC_SHIFT 0
#define DIO_CYC0_CYC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_CYC0_CYC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio 1 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 1 seconds-based trigger for pulse generation */
#define DIO_TRIG1_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TRIG1_SECONDS_SHIFT 0
#define DIO_TRIG1_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TRIG1_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: fmc-dio 1 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 1 seconds-based trigger for pulse generation */
#define DIO_TRIGH1_SECONDS_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TRIGH1_SECONDS_SHIFT 0
#define DIO_TRIGH1_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TRIGH1_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: fmc-dio 1 cycles to trigger a pulse generation */
/* definitions for field: cycles field in reg: fmc-dio 1 cycles to trigger a pulse generation */
#define DIO_CYC1_CYC_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_CYC1_CYC_SHIFT 0
#define DIO_CYC1_CYC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_CYC1_CYC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio 2 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 2 seconds-based trigger for pulse generation */
#define DIO_TRIG2_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TRIG2_SECONDS_SHIFT 0
#define DIO_TRIG2_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TRIG2_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: fmc-dio 2 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 2 seconds-based trigger for pulse generation */
#define DIO_TRIGH2_SECONDS_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TRIGH2_SECONDS_SHIFT 0
#define DIO_TRIGH2_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TRIGH2_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: fmc-dio 2 cycles to trigger a pulse generation */
/* definitions for field: cycles field in reg: fmc-dio 2 cycles to trigger a pulse generation */
#define DIO_CYC2_CYC_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_CYC2_CYC_SHIFT 0
#define DIO_CYC2_CYC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_CYC2_CYC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio 3 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 3 seconds-based trigger for pulse generation */
#define DIO_TRIG3_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TRIG3_SECONDS_SHIFT 0
#define DIO_TRIG3_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TRIG3_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: fmc-dio 3 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 3 seconds-based trigger for pulse generation */
#define DIO_TRIGH3_SECONDS_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TRIGH3_SECONDS_SHIFT 0
#define DIO_TRIGH3_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TRIGH3_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: fmc-dio 3 cycles to trigger a pulse generation */
/* definitions for field: cycles field in reg: fmc-dio 3 cycles to trigger a pulse generation */
#define DIO_CYC3_CYC_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_CYC3_CYC_SHIFT 0
#define DIO_CYC3_CYC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_CYC3_CYC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio 4 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 4 seconds-based trigger for pulse generation */
#define DIO_TRIG4_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TRIG4_SECONDS_SHIFT 0
#define DIO_TRIG4_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TRIG4_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: fmc-dio 4 seconds-based trigger for pulse generation */
/* definitions for field: seconds field in reg: fmc-dio 4 seconds-based trigger for pulse generation */
#define DIO_TRIGH4_SECONDS_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TRIGH4_SECONDS_SHIFT 0
#define DIO_TRIGH4_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TRIGH4_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: fmc-dio 4 cycles to trigger a pulse generation */
/* definitions for field: cycles field in reg: fmc-dio 4 cycles to trigger a pulse generation */
#define DIO_CYC4_CYC_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_CYC4_CYC_SHIFT 0
#define DIO_CYC4_CYC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_CYC4_CYC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FMC-DIO input/output configuration register. */
/* definitions for field: channel0 in reg: FMC-DIO input/output configuration register. */
#define DIO_IOMODE_CH0_MASK WBGEN2_GEN_MASK(0, 4)
#define DIO_IOMODE_CH0_SHIFT 0
#define DIO_IOMODE_CH0_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define DIO_IOMODE_CH0_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: channel1 in reg: FMC-DIO input/output configuration register. */
#define DIO_IOMODE_CH1_MASK WBGEN2_GEN_MASK(4, 4)
#define DIO_IOMODE_CH1_SHIFT 4
#define DIO_IOMODE_CH1_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define DIO_IOMODE_CH1_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: channel2 in reg: FMC-DIO input/output configuration register. */
#define DIO_IOMODE_CH2_MASK WBGEN2_GEN_MASK(8, 4)
#define DIO_IOMODE_CH2_SHIFT 8
#define DIO_IOMODE_CH2_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DIO_IOMODE_CH2_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: channel3 in reg: FMC-DIO input/output configuration register. */
#define DIO_IOMODE_CH3_MASK WBGEN2_GEN_MASK(12, 4)
#define DIO_IOMODE_CH3_SHIFT 12
#define DIO_IOMODE_CH3_W(value) WBGEN2_GEN_WRITE(value, 12, 4)
#define DIO_IOMODE_CH3_R(reg) WBGEN2_GEN_READ(reg, 12, 4)
/* definitions for field: channel4 in reg: FMC-DIO input/output configuration register. */
#define DIO_IOMODE_CH4_MASK WBGEN2_GEN_MASK(16, 4)
#define DIO_IOMODE_CH4_SHIFT 16
#define DIO_IOMODE_CH4_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define DIO_IOMODE_CH4_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for register: Time-programmable output strobe signal */
/* definitions for field: Sincle-cycle strobe in reg: Time-programmable output strobe signal */
#define DIO_LATCH_TIME_CH0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Sincle-cycle strobe in reg: Time-programmable output strobe signal */
#define DIO_LATCH_TIME_CH1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Sincle-cycle strobe in reg: Time-programmable output strobe signal */
#define DIO_LATCH_TIME_CH2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Sincle-cycle strobe in reg: Time-programmable output strobe signal */
#define DIO_LATCH_TIME_CH3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Sincle-cycle strobe in reg: Time-programmable output strobe signal */
#define DIO_LATCH_TIME_CH4 WBGEN2_GEN_MASK(4, 1)
/* definitions for register: FMC-DIO time trigger is ready to accept a new trigger generation request */
/* definitions for field: trig_rdy field in reg: FMC-DIO time trigger is ready to accept a new trigger generation request */
#define DIO_TRIG_RDY_MASK WBGEN2_GEN_MASK(0, 5)
#define DIO_TRIG_RDY_SHIFT 0
#define DIO_TRIG_RDY_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define DIO_TRIG_RDY_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for register: fmc-dio channel 0 Programmable/immediate output pulse length */
/* definitions for field: number of ticks field for channel 0 in reg: fmc-dio channel 0 Programmable/immediate output pulse length */
#define DIO_PROG0_PULSE_LENGTH_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_PROG0_PULSE_LENGTH_SHIFT 0
#define DIO_PROG0_PULSE_LENGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_PROG0_PULSE_LENGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio channel 1 Programmable/immediate output pulse length */
/* definitions for field: number of ticks field for channel 1 in reg: fmc-dio channel 1 Programmable/immediate output pulse length */
#define DIO_PROG1_PULSE_LENGTH_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_PROG1_PULSE_LENGTH_SHIFT 0
#define DIO_PROG1_PULSE_LENGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_PROG1_PULSE_LENGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio channel 2 Programmable/immediate output pulse length */
/* definitions for field: number of ticks field for channel 2 in reg: fmc-dio channel 2 Programmable/immediate output pulse length */
#define DIO_PROG2_PULSE_LENGTH_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_PROG2_PULSE_LENGTH_SHIFT 0
#define DIO_PROG2_PULSE_LENGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_PROG2_PULSE_LENGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio channel 3 Programmable/immediate output pulse length */
/* definitions for field: number of ticks field for channel 3 in reg: fmc-dio channel 3 Programmable/immediate output pulse length */
#define DIO_PROG3_PULSE_LENGTH_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_PROG3_PULSE_LENGTH_SHIFT 0
#define DIO_PROG3_PULSE_LENGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_PROG3_PULSE_LENGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: fmc-dio channel 4 Programmable/immediate output pulse length */
/* definitions for field: number of ticks field for channel 4 in reg: fmc-dio channel 4 Programmable/immediate output pulse length */
#define DIO_PROG4_PULSE_LENGTH_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_PROG4_PULSE_LENGTH_SHIFT 0
#define DIO_PROG4_PULSE_LENGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_PROG4_PULSE_LENGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Pulse generate immediately */
/* definitions for field: pulse_gen_now_0 in reg: Pulse generate immediately */
#define DIO_PULSE_IMM_0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: pulse_gen_now_1 in reg: Pulse generate immediately */
#define DIO_PULSE_IMM_1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: pulse_gen_now_2 in reg: Pulse generate immediately */
#define DIO_PULSE_IMM_2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: pulse_gen_now_3 in reg: Pulse generate immediately */
#define DIO_PULSE_IMM_3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: pulse_gen_now_4 in reg: Pulse generate immediately */
#define DIO_PULSE_IMM_4 WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: dio fifo not-empty 0 in reg: Interrupt disable register */
#define DIO_EIC_IDR_NEMPTY_0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: dio fifo not-empty 1 in reg: Interrupt disable register */
#define DIO_EIC_IDR_NEMPTY_1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: dio fifo not-empty 2 in reg: Interrupt disable register */
#define DIO_EIC_IDR_NEMPTY_2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: dio fifo not-empty 3 in reg: Interrupt disable register */
#define DIO_EIC_IDR_NEMPTY_3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: dio fifo not-empty 4 in reg: Interrupt disable register */
#define DIO_EIC_IDR_NEMPTY_4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 0 trigger ready interrupt in reg: Interrupt disable register */
#define DIO_EIC_IDR_TRIGGER_READY_0 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 trigger ready interrupt in reg: Interrupt disable register */
#define DIO_EIC_IDR_TRIGGER_READY_1 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Channel 2 trigger ready interrupt in reg: Interrupt disable register */
#define DIO_EIC_IDR_TRIGGER_READY_2 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Channel 3 trigger ready interrupt in reg: Interrupt disable register */
#define DIO_EIC_IDR_TRIGGER_READY_3 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 4 trigger ready interrupt in reg: Interrupt disable register */
#define DIO_EIC_IDR_TRIGGER_READY_4 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: dio fifo not-empty 0 in reg: Interrupt enable register */
#define DIO_EIC_IER_NEMPTY_0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: dio fifo not-empty 1 in reg: Interrupt enable register */
#define DIO_EIC_IER_NEMPTY_1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: dio fifo not-empty 2 in reg: Interrupt enable register */
#define DIO_EIC_IER_NEMPTY_2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: dio fifo not-empty 3 in reg: Interrupt enable register */
#define DIO_EIC_IER_NEMPTY_3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: dio fifo not-empty 4 in reg: Interrupt enable register */
#define DIO_EIC_IER_NEMPTY_4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 0 trigger ready interrupt in reg: Interrupt enable register */
#define DIO_EIC_IER_TRIGGER_READY_0 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 trigger ready interrupt in reg: Interrupt enable register */
#define DIO_EIC_IER_TRIGGER_READY_1 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Channel 2 trigger ready interrupt in reg: Interrupt enable register */
#define DIO_EIC_IER_TRIGGER_READY_2 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Channel 3 trigger ready interrupt in reg: Interrupt enable register */
#define DIO_EIC_IER_TRIGGER_READY_3 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 4 trigger ready interrupt in reg: Interrupt enable register */
#define DIO_EIC_IER_TRIGGER_READY_4 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: dio fifo not-empty 0 in reg: Interrupt mask register */
#define DIO_EIC_IMR_NEMPTY_0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: dio fifo not-empty 1 in reg: Interrupt mask register */
#define DIO_EIC_IMR_NEMPTY_1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: dio fifo not-empty 2 in reg: Interrupt mask register */
#define DIO_EIC_IMR_NEMPTY_2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: dio fifo not-empty 3 in reg: Interrupt mask register */
#define DIO_EIC_IMR_NEMPTY_3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: dio fifo not-empty 4 in reg: Interrupt mask register */
#define DIO_EIC_IMR_NEMPTY_4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 0 trigger ready interrupt in reg: Interrupt mask register */
#define DIO_EIC_IMR_TRIGGER_READY_0 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 trigger ready interrupt in reg: Interrupt mask register */
#define DIO_EIC_IMR_TRIGGER_READY_1 WBGEN2_GEN_MASK(6, 1)
struct
regmap
{
int
trig_l
;
int
trig_h
;
int
cycle
;
int
pulse
;
int
pulse_per
;
int
fifo_tai_l
;
int
fifo_tai_h
;
int
fifo_cycle
;
int
fifo_status
;
};
/* definitions for field: Channel 2 trigger ready interrupt in reg: Interrupt mask register */
#define DIO_EIC_IMR_TRIGGER_READY_2 WBGEN2_GEN_MASK(7, 1)
struct
regmap_common
{
int
ver_
;
int
iomode_reg
;
int
latch_reg
;
int
trig_reg
;
int
pulse_reg
;
int
eic_idr_reg
;
int
eic_ier_reg
;
int
eic_imr_reg
;
int
eic_isr_reg
;
};
/* definitions for field: Channel 3 trigger ready interrupt in reg: Interrupt mask register */
#define DIO_EIC_IMR_TRIGGER_READY_3 WBGEN2_GEN_MASK(8, 1)
extern
struct
regmap
regmap_v1
[];
extern
struct
regmap
regmap_v2
[];
/* definitions for field: Channel 4 trigger ready interrupt in reg: Interrupt mask register */
#define DIO_EIC_IMR_TRIGGER_READY_4 WBGEN2_GEN_MASK(9, 1)
extern
struct
regmap_common
regmap_common_v1
;
extern
struct
regmap_common
regmap_common_v2
;
/* definitions for register: Interrupt status register */
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
/* definitions for field: dio fifo not-empty 0 in reg: Interrupt status register */
#define DIO_EIC_ISR_NEMPTY_0 WBGEN2_GEN_MASK(0, 1)
...
...
@@ -382,308 +61,10 @@
/* definitions for field: dio fifo not-empty 4 in reg: Interrupt status register */
#define DIO_EIC_ISR_NEMPTY_4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 0 trigger ready interrupt in reg: Interrupt status register */
#define DIO_EIC_ISR_TRIGGER_READY_0 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 trigger ready interrupt in reg: Interrupt status register */
#define DIO_EIC_ISR_TRIGGER_READY_1 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Channel 2 trigger ready interrupt in reg: Interrupt status register */
#define DIO_EIC_ISR_TRIGGER_READY_2 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Channel 3 trigger ready interrupt in reg: Interrupt status register */
#define DIO_EIC_ISR_TRIGGER_READY_3 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 4 trigger ready interrupt in reg: Interrupt status register */
#define DIO_EIC_ISR_TRIGGER_READY_4 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: FIFO 'Timestamp FIFO 0' data output register 0 */
/* definitions for field: seconds time in reg: FIFO 'Timestamp FIFO 0' data output register 0 */
#define DIO_TSF0_R0_TAG_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TSF0_R0_TAG_SECONDS_SHIFT 0
#define DIO_TSF0_R0_TAG_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TSF0_R0_TAG_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO 0' data output register 1 */
/* definitions for field: seconds time H in reg: FIFO 'Timestamp FIFO 0' data output register 1 */
#define DIO_TSF0_R1_TAG_SECONDSH_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF0_R1_TAG_SECONDSH_SHIFT 0
#define DIO_TSF0_R1_TAG_SECONDSH_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF0_R1_TAG_SECONDSH_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 0' data output register 2 */
/* definitions for field: Sub-second accuracy in reg: FIFO 'Timestamp FIFO 0' data output register 2 */
#define DIO_TSF0_R2_TAG_CYCLES_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_TSF0_R2_TAG_CYCLES_SHIFT 0
#define DIO_TSF0_R2_TAG_CYCLES_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_TSF0_R2_TAG_CYCLES_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FIFO 'Timestamp FIFO 0' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO 0' control/status register */
#define DIO_TSF0_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO 0' control/status register */
#define DIO_TSF0_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO 0' control/status register */
#define DIO_TSF0_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF0_CSR_USEDW_SHIFT 0
#define DIO_TSF0_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF0_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 1' data output register 0 */
/* definitions for field: seconds time in reg: FIFO 'Timestamp FIFO 1' data output register 0 */
#define DIO_TSF1_R0_TAG_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TSF1_R0_TAG_SECONDS_SHIFT 0
#define DIO_TSF1_R0_TAG_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TSF1_R0_TAG_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO 1' data output register 1 */
/* definitions for field: dio fifo not-empty 5 in reg: Interrupt status register */
#define DIO_EIC_ISR_NEMPTY_5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: seconds time H in reg: FIFO 'Timestamp FIFO 1' data output register 1 */
#define DIO_TSF1_R1_TAG_SECONDSH_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF1_R1_TAG_SECONDSH_SHIFT 0
#define DIO_TSF1_R1_TAG_SECONDSH_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF1_R1_TAG_SECONDSH_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
struct
regmap_common
get_regmap_common
(
unsigned
int
ver
);
struct
regmap
*
get_regmap
(
unsigned
int
ver
);
/* definitions for register: FIFO 'Timestamp FIFO 1' data output register 2 */
/* definitions for field: Sub-second accuracy in reg: FIFO 'Timestamp FIFO 1' data output register 2 */
#define DIO_TSF1_R2_TAG_CYCLES_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_TSF1_R2_TAG_CYCLES_SHIFT 0
#define DIO_TSF1_R2_TAG_CYCLES_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_TSF1_R2_TAG_CYCLES_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FIFO 'Timestamp FIFO 1' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO 1' control/status register */
#define DIO_TSF1_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO 1' control/status register */
#define DIO_TSF1_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO 1' control/status register */
#define DIO_TSF1_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF1_CSR_USEDW_SHIFT 0
#define DIO_TSF1_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF1_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 2' data output register 0 */
/* definitions for field: seconds time in reg: FIFO 'Timestamp FIFO 2' data output register 0 */
#define DIO_TSF2_R0_TAG_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TSF2_R0_TAG_SECONDS_SHIFT 0
#define DIO_TSF2_R0_TAG_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TSF2_R0_TAG_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO 2' data output register 1 */
/* definitions for field: seconds time H in reg: FIFO 'Timestamp FIFO 2' data output register 1 */
#define DIO_TSF2_R1_TAG_SECONDSH_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF2_R1_TAG_SECONDSH_SHIFT 0
#define DIO_TSF2_R1_TAG_SECONDSH_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF2_R1_TAG_SECONDSH_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 2' data output register 2 */
/* definitions for field: Sub-second accuracy in reg: FIFO 'Timestamp FIFO 2' data output register 2 */
#define DIO_TSF2_R2_TAG_CYCLES_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_TSF2_R2_TAG_CYCLES_SHIFT 0
#define DIO_TSF2_R2_TAG_CYCLES_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_TSF2_R2_TAG_CYCLES_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FIFO 'Timestamp FIFO 2' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO 2' control/status register */
#define DIO_TSF2_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO 2' control/status register */
#define DIO_TSF2_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO 2' control/status register */
#define DIO_TSF2_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF2_CSR_USEDW_SHIFT 0
#define DIO_TSF2_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF2_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 3' data output register 0 */
/* definitions for field: seconds time in reg: FIFO 'Timestamp FIFO 3' data output register 0 */
#define DIO_TSF3_R0_TAG_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TSF3_R0_TAG_SECONDS_SHIFT 0
#define DIO_TSF3_R0_TAG_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TSF3_R0_TAG_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO 3' data output register 1 */
/* definitions for field: seconds time H in reg: FIFO 'Timestamp FIFO 3' data output register 1 */
#define DIO_TSF3_R1_TAG_SECONDSH_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF3_R1_TAG_SECONDSH_SHIFT 0
#define DIO_TSF3_R1_TAG_SECONDSH_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF3_R1_TAG_SECONDSH_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 3' data output register 2 */
/* definitions for field: Sub-second accuracy in reg: FIFO 'Timestamp FIFO 3' data output register 2 */
#define DIO_TSF3_R2_TAG_CYCLES_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_TSF3_R2_TAG_CYCLES_SHIFT 0
#define DIO_TSF3_R2_TAG_CYCLES_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_TSF3_R2_TAG_CYCLES_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FIFO 'Timestamp FIFO 3' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO 3' control/status register */
#define DIO_TSF3_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO 3' control/status register */
#define DIO_TSF3_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO 3' control/status register */
#define DIO_TSF3_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF3_CSR_USEDW_SHIFT 0
#define DIO_TSF3_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF3_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 4' data output register 0 */
/* definitions for field: seconds time in reg: FIFO 'Timestamp FIFO 4' data output register 0 */
#define DIO_TSF4_R0_TAG_SECONDS_MASK WBGEN2_GEN_MASK(0, 32)
#define DIO_TSF4_R0_TAG_SECONDS_SHIFT 0
#define DIO_TSF4_R0_TAG_SECONDS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DIO_TSF4_R0_TAG_SECONDS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO 4' data output register 1 */
/* definitions for field: seconds time H in reg: FIFO 'Timestamp FIFO 4' data output register 1 */
#define DIO_TSF4_R1_TAG_SECONDSH_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF4_R1_TAG_SECONDSH_SHIFT 0
#define DIO_TSF4_R1_TAG_SECONDSH_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF4_R1_TAG_SECONDSH_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'Timestamp FIFO 4' data output register 2 */
/* definitions for field: Sub-second accuracy in reg: FIFO 'Timestamp FIFO 4' data output register 2 */
#define DIO_TSF4_R2_TAG_CYCLES_MASK WBGEN2_GEN_MASK(0, 28)
#define DIO_TSF4_R2_TAG_CYCLES_SHIFT 0
#define DIO_TSF4_R2_TAG_CYCLES_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define DIO_TSF4_R2_TAG_CYCLES_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: FIFO 'Timestamp FIFO 4' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO 4' control/status register */
#define DIO_TSF4_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO 4' control/status register */
#define DIO_TSF4_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO 4' control/status register */
#define DIO_TSF4_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DIO_TSF4_CSR_USEDW_SHIFT 0
#define DIO_TSF4_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DIO_TSF4_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED
struct
DIO_WB
{
/* [0x0]: REG fmc-dio 0 seconds-based trigger for pulse generation */
uint32_t
TRIG0
;
/* [0x4]: REG fmc-dio 0 seconds-based trigger for pulse generation */
uint32_t
TRIGH0
;
/* [0x8]: REG fmc-dio 0 cycles to trigger a pulse generation */
uint32_t
CYC0
;
/* [0xc]: REG fmc-dio 1 seconds-based trigger for pulse generation */
uint32_t
TRIG1
;
/* [0x10]: REG fmc-dio 1 seconds-based trigger for pulse generation */
uint32_t
TRIGH1
;
/* [0x14]: REG fmc-dio 1 cycles to trigger a pulse generation */
uint32_t
CYC1
;
/* [0x18]: REG fmc-dio 2 seconds-based trigger for pulse generation */
uint32_t
TRIG2
;
/* [0x1c]: REG fmc-dio 2 seconds-based trigger for pulse generation */
uint32_t
TRIGH2
;
/* [0x20]: REG fmc-dio 2 cycles to trigger a pulse generation */
uint32_t
CYC2
;
/* [0x24]: REG fmc-dio 3 seconds-based trigger for pulse generation */
uint32_t
TRIG3
;
/* [0x28]: REG fmc-dio 3 seconds-based trigger for pulse generation */
uint32_t
TRIGH3
;
/* [0x2c]: REG fmc-dio 3 cycles to trigger a pulse generation */
uint32_t
CYC3
;
/* [0x30]: REG fmc-dio 4 seconds-based trigger for pulse generation */
uint32_t
TRIG4
;
/* [0x34]: REG fmc-dio 4 seconds-based trigger for pulse generation */
uint32_t
TRIGH4
;
/* [0x38]: REG fmc-dio 4 cycles to trigger a pulse generation */
uint32_t
CYC4
;
/* [0x3c]: REG FMC-DIO input/output configuration register. */
uint32_t
IOMODE
;
/* [0x40]: REG Time-programmable output strobe signal */
uint32_t
R_LATCH
;
/* [0x44]: REG FMC-DIO time trigger is ready to accept a new trigger generation request */
uint32_t
TRIG
;
/* [0x48]: REG fmc-dio channel 0 Programmable/immediate output pulse length */
uint32_t
PROG0_PULSE
;
/* [0x4c]: REG fmc-dio channel 1 Programmable/immediate output pulse length */
uint32_t
PROG1_PULSE
;
/* [0x50]: REG fmc-dio channel 2 Programmable/immediate output pulse length */
uint32_t
PROG2_PULSE
;
/* [0x54]: REG fmc-dio channel 3 Programmable/immediate output pulse length */
uint32_t
PROG3_PULSE
;
/* [0x58]: REG fmc-dio channel 4 Programmable/immediate output pulse length */
uint32_t
PROG4_PULSE
;
/* [0x5c]: REG Pulse generate immediately */
uint32_t
PULSE
;
/* [0x60]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0x64]: REG Interrupt enable register */
uint32_t
EIC_IER
;
/* [0x68]: REG Interrupt mask register */
uint32_t
EIC_IMR
;
/* [0x6c]: REG Interrupt status register */
uint32_t
EIC_ISR
;
/* [0x70]: REG FIFO 'Timestamp FIFO 0' data output register 0 */
uint32_t
TSF0_R0
;
/* [0x74]: REG FIFO 'Timestamp FIFO 0' data output register 1 */
uint32_t
TSF0_R1
;
/* [0x78]: REG FIFO 'Timestamp FIFO 0' data output register 2 */
uint32_t
TSF0_R2
;
/* [0x7c]: REG FIFO 'Timestamp FIFO 0' control/status register */
uint32_t
TSF0_CSR
;
/* [0x80]: REG FIFO 'Timestamp FIFO 1' data output register 0 */
uint32_t
TSF1_R0
;
/* [0x84]: REG FIFO 'Timestamp FIFO 1' data output register 1 */
uint32_t
TSF1_R1
;
/* [0x88]: REG FIFO 'Timestamp FIFO 1' data output register 2 */
uint32_t
TSF1_R2
;
/* [0x8c]: REG FIFO 'Timestamp FIFO 1' control/status register */
uint32_t
TSF1_CSR
;
/* [0x90]: REG FIFO 'Timestamp FIFO 2' data output register 0 */
uint32_t
TSF2_R0
;
/* [0x94]: REG FIFO 'Timestamp FIFO 2' data output register 1 */
uint32_t
TSF2_R1
;
/* [0x98]: REG FIFO 'Timestamp FIFO 2' data output register 2 */
uint32_t
TSF2_R2
;
/* [0x9c]: REG FIFO 'Timestamp FIFO 2' control/status register */
uint32_t
TSF2_CSR
;
/* [0xa0]: REG FIFO 'Timestamp FIFO 3' data output register 0 */
uint32_t
TSF3_R0
;
/* [0xa4]: REG FIFO 'Timestamp FIFO 3' data output register 1 */
uint32_t
TSF3_R1
;
/* [0xa8]: REG FIFO 'Timestamp FIFO 3' data output register 2 */
uint32_t
TSF3_R2
;
/* [0xac]: REG FIFO 'Timestamp FIFO 3' control/status register */
uint32_t
TSF3_CSR
;
/* [0xb0]: REG FIFO 'Timestamp FIFO 4' data output register 0 */
uint32_t
TSF4_R0
;
/* [0xb4]: REG FIFO 'Timestamp FIFO 4' data output register 1 */
uint32_t
TSF4_R1
;
/* [0xb8]: REG FIFO 'Timestamp FIFO 4' data output register 2 */
uint32_t
TSF4_R2
;
/* [0xbc]: REG FIFO 'Timestamp FIFO 4' control/status register */
uint32_t
TSF4_CSR
;
};
#endif
#endif
\ No newline at end of file
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