Commit 76f580f8 authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez

hdl: Move and rename DIO modules and testbench.

parent 854b0a92
files = ["wrsw_dio_wb.vhd",
"xwrsw_dio.vhd",
"wrsw_dio.vhd",
"wrnic_sdb_pkg.vhd",
files = ["wr_dio_wb.vhd",
"xwr_dio.vhd",
"wr_dio.vhd",
"wr_dio_pkg.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
......
#!/bin/bash
wbgen2 -D wr_dio_wb.htm -V wr_dio_wb.vhd --cstyle defines --lang vhdl -K ../../sim/dio_timing_regs.vh wr_dio.wb
-------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n: in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n: in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond: std_logic;
signal init_time: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
signal init_time: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
oneSecond <= '0';
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others=>'0');
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others=>'0');
end if;
if(Tm_cycles_Aux = MaxCountcycles1) then
OneSecond <= '1';
OneSecond <= '1';
else
OneSecond <= '0';
end if;
init_time <= '1';
end if;
end process P_CountTM_cycles;
P_CountTM_UTC:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others=>'0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond='1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others=>'0');
end if;
OneSecond <= '0';
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
end Behavioral;
init_time <= '1';
end if;
end process P_CountTM_cycles;
P_CountTM_UTC:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others=>'0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond='1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others=>'0');
end if;
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
end Behavioral;
......@@ -2,7 +2,7 @@
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : wrsw_dio.vhd
-- File : wr_dio.vhd
-- Author : Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-07-25
......@@ -10,7 +10,7 @@
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Simulation file for the xwrsw_dio.vhd file
-- Description: Simulation file for the xwr_dio.vhd file
--
-------------------------------------------------------------------------------
-- TODO:
......@@ -29,7 +29,7 @@ library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity wrsw_dio is
entity wr_dio is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -54,6 +54,7 @@ entity wrsw_dio is
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
dio_ga_o : out std_logic_vector(1 downto 0);
dio_int : out std_logic;
tm_time_valid_i : in std_logic;
tm_seconds_i : in std_logic_vector(39 downto 0);
......@@ -80,13 +81,13 @@ entity wrsw_dio is
TRIG3 : out std_logic_vector(31 downto 0)
);
end wrsw_dio;
end wr_dio;
architecture rtl of wrsw_dio is
architecture rtl of wr_dio is
-- DIO core
component xwrsw_dio
component xwr_dio
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -122,7 +123,8 @@ architecture rtl of wrsw_dio is
TRIG3 : out std_logic_vector(31 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
slave_o : out t_wishbone_slave_out;
dio_int : out std_logic
);
end component; --DIO core
......@@ -131,7 +133,7 @@ architecture rtl of wrsw_dio is
-------------------------------------------------------------------------------
begin
U_WRAPPER_DIO : xwrsw_dio
U_WRAPPER_DIO : xwr_dio
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
......@@ -163,7 +165,9 @@ U_WRAPPER_DIO : xwrsw_dio
tm_cycles_i => tm_cycles_i,
slave_i => wb_in,
slave_o => wb_out
slave_o => wb_out,
dio_int => dio_int
-- Chipscope, debugging signals
--TRIG0 => TRIG0,
......@@ -181,8 +185,6 @@ U_WRAPPER_DIO : xwrsw_dio
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_irq_o <= wb_out.int;
-----------------------------------------------------------------------------------
end rtl;
......
......@@ -32,7 +32,7 @@ peripheral {
prefix="dio";
hdl_entity="wrsw_dio_wb";
hdl_entity="wr_dio_wb";
----------------------------------------------------
-- FIFOS & INTERRUPTS FOR INPUT EVENT TIME STAMPING
......
......@@ -30,60 +30,12 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package wrnic_sdb_pkg is
package wr_dio_pkg is
-----------------------------------------------------------------------------
-- WR CORE --> TBD: move to wrcore_pkg
-- DIO
-----------------------------------------------------------------------------
constant c_xwr_core_sdb : t_sdb_product := (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000011",
version => x"00000003",
date => x"20120305",
name => "WR-CORE ");
-----------------------------------------------------------------------------
-- WR NIC
-----------------------------------------------------------------------------
constant c_xwrsw_nic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000001ffff", -- I think this is overestimated
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000012",
version => x"00000001",
date => x"20000101", -- UNKNOWN
name => "WR-NIC ")));
-----------------------------------------------------------------------------
-- WR TXTSU --> TBD: Move to wrsw_txtsu_pkg
-----------------------------------------------------------------------------
constant c_xwrsw_txtsu_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000014",
version => x"00000001",
date => x"20120316",
name => "WR-TXTSU ")));
-----------------------------------------------------------------------------
-- WRSW DIO
-----------------------------------------------------------------------------
constant c_xwrsw_dio_sdb : t_sdb_product := (
constant c_xwr_dio_sdb : t_sdb_product := (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000002",
version => x"00000002",
......@@ -91,9 +43,9 @@ package wrnic_sdb_pkg is
name => "WR-DIO-Core ");
-----------------------------------------------------------------------------
-- WRSW DIO REGISTERS - (basic slave from wbgen2)
-- DIO REGISTERS - (basic slave from wbgen2)
-----------------------------------------------------------------------------
constant c_xwrsw_dio_wb_sdb : t_sdb_device := (
constant c_xwr_dio_wb_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -109,70 +61,6 @@ package wrnic_sdb_pkg is
date => x"20120709",
name => "WR-DIO-Registers ")));
-------------------------------------------------------------------------------
-- WB ONEWIRE MASTER --> TBD: move wishbone_pkg
-- ISSUE: this element have two sdb definitions with different names, this one
-- and the one available at WR_CORE_PKG.
-- The definition need to be unique and be included into wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_onewire_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"779c5443",
-- version => x"00000001",
-- date => x"20120305",
-- name => "WR-1Wire-master ")));
-------------------------------------------------------------------------------
-- WB I2C MASTER --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_i2c_master_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"123c5443",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-I2C-Master ")));
-------------------------------------------------------------------------------
-- WB GPIO --> TBD: move to wishbone_pkg
-------------------------------------------------------------------------------
-- constant c_xwb_gpio_port_sdb : t_sdb_device := (
-- abi_class => x"0000", -- undocumented device
-- abi_ver_major => x"01",
-- abi_ver_minor => x"01",
-- wbd_endian => c_sdb_endian_big,
-- wbd_width => x"7", -- 8/16/32-bit port granularity
-- sdb_component => (
-- addr_first => x"0000000000000000",
-- addr_last => x"00000000000000ff",
-- product => (
-- vendor_id => x"000000000000CE42", -- CERN
-- device_id => x"441c5143",
-- version => x"00000001",
-- date => x"20000101", -- UNKNOWN
-- name => "WB-GPIO-Port ")));
------------------------------------------------------------------------------
-- SDB re-declaration of bridges function to include product info
------------------------------------------------------------------------------
......@@ -190,9 +78,9 @@ package wrnic_sdb_pkg is
g_sdb_product : t_sdb_product) return t_sdb_bridge;
end wrnic_sdb_pkg;
end wr_dio_pkg;
package body wrnic_sdb_pkg is
package body wr_dio_pkg is
function f_xwb_bridge_product_manual_sdb(
g_size : t_wishbone_address;
......@@ -266,6 +154,4 @@ package body wrnic_sdb_pkg is
return f_xwb_bridge_product_manual_sdb(std_logic_vector(f_bus_end(c_wishbone_address_width-1 downto 0)), g_sdb_addr, g_sdb_product);
end f_xwb_bridge_product_layout_sdb;
end wrnic_sdb_pkg;
end wr_dio_pkg;
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC-DIO-5chttla
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- File : wr_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wr_dio.wb
-- Created : Wed May 8 14:07:08 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_dio.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -15,7 +15,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wrsw_dio_wb is
entity wr_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -168,9 +168,9 @@ entity wrsw_dio_wb is
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic
);
end wrsw_dio_wb;
end wr_dio_wb;
architecture syn of wrsw_dio_wb is
architecture syn of wr_dio_wb is
signal dio_tsf0_rst_n : std_logic ;
signal dio_tsf0_in_int : std_logic_vector(67 downto 0);
......
......@@ -2,7 +2,7 @@
-- Title : DIO Core
-- Project : White Rabbit Network Interface
-------------------------------------------------------------------------------
-- File : xwrsw_dio.vhd
-- File : xwr_dio.vhd
-- Author : Rafael Rodriguez, Javier Díaz
-- Company : Seven Solutions
-- Created : 2012-03-03
......@@ -22,8 +22,8 @@
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.1 JDiaz Added wrsw_dio_wb
-- 2012-07-05 0.2 JDiaz Modified wrsw_dio_wb, modified interface
-- 2012-03-08 0.1 JDiaz Added wr_dio_wb
-- 2012-07-05 0.2 JDiaz Modified wr_dio_wb, modified interface
-- 2012-07-20 0.2 JDiaz Include sdb support
-------------------------------------------------------------------------------
-- Memory map:
......@@ -39,9 +39,9 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.wrnic_sdb_pkg.all;
use work.wr_dio_pkg.all;
entity xwrsw_dio is
entity xwr_dio is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -73,6 +73,8 @@ entity xwrsw_dio is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dio_int : out std_logic;
-- Debug signals for chipscope
TRIG0 : out std_logic_vector(31 downto 0);
......@@ -80,10 +82,10 @@ entity xwrsw_dio is
TRIG2 : out std_logic_vector(31 downto 0);
TRIG3 : out std_logic_vector(31 downto 0)
);
end xwrsw_dio;
end xwr_dio;
architecture rtl of xwrsw_dio is
architecture rtl of xwr_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
......@@ -189,7 +191,7 @@ architecture rtl of xwrsw_dio is
);
end component;
component wrsw_dio_wb is
component wr_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -399,7 +401,7 @@ architecture rtl of xwrsw_dio is
(0 => f_sdb_embed_device(c_xwb_onewire_master_sdb , x"00000000"), -- ONEWIRE
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb , x"00000100"), -- I2C
2 => f_sdb_embed_device(c_xwb_gpio_port_sdb , x"00000200"), -- GPIO
3 => f_sdb_embed_device(c_xwrsw_dio_wb_sdb , x"00000300") -- DIO REGISTERS
3 => f_sdb_embed_device(c_xwr_dio_wb_sdb , x"00000300") -- DIO REGISTERS
);
constant c_diobar_sdb_address : t_wishbone_address := x"00000400";
......@@ -529,12 +531,12 @@ begin
slave_i => cbar_master_out(1),
slave_o => cbar_master_in(1),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
scl_pad_i(0) => scl_pad_in,
scl_pad_o(0) => scl_pad_out,
scl_padoen_o(0) => scl_pad_oen,
sda_pad_i(0) => sda_pad_in,
sda_pad_o(0) => sda_pad_out,
sda_padoen_o(0) => sda_pad_oen);
dio_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
......@@ -597,7 +599,8 @@ begin
slave_o.ack <= slave_bypass_o.ack;
slave_o.stall <= slave_bypass_o.stall;
slave_o.int <= wb_dio_irq;
--slave_o.int <= wb_dio_irq;
dio_int <= wb_dio_irq;
slave_o.dat <= slave_bypass_o.dat;
slave_o.err <= slave_bypass_o.err;
slave_o.rty <= slave_bypass_o.rty;
......@@ -680,10 +683,9 @@ begin
------------------------------------------------------------------------------
wb_dio_slave_out.err<='0';
wb_dio_slave_out.rty<='0';
wb_dio_slave_out.int<='0'; -- Real signal we bypass to crossbar
-- SUPPORTING PIPELINE WBGEN2 SLAVES
U_DIO_REGISTERS : wrsw_dio_wb
U_DIO_REGISTERS : wr_dio_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -862,7 +864,6 @@ begin
TRIG0(23) <= tm_time_valid_i;
TRIG0(31 downto 24) <= pulse_length(0)(7 downto 0);
TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
TRIG1(28) <= slave_bypass_o.int;
TRIG1(29) <= slave_bypass_o.ack;
TRIG1(30) <= dio_pulse(0);
TRIG1(31) <= gpio_out(0);
......
......@@ -31,7 +31,7 @@ module main;
//assign #10 clk_sys_dly = clk_sys;
//assign #10ns time_valid =1'b1;
wrsw_dio
wr_dio
#(
.g_interface_mode(PIPELINED),
.g_address_granularity(WORD))
......
#!/bin/bash
wbgen2 -D wrsw_dio_wb.htm -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
#mkdir -p doc
# wbgen2 -D ./doc/dio.html -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -p dio_wbgen2_pkg.vhd -H record -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
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