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FMC DIO 5ch TTL a
Commit 87566221 authored by Javier Díaz's avatar Javier Díaz Committed by Miguel Jimenez Lopez
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pipelined wb slaves and dio adapter

parent fa62367d
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Showing with 41 additions and 25 deletions
testbench/wrsw_dio/main.sv
View file @ 87566221
...@@ -11,8 +11,9 @@ module main; ...@@ -11,8 +11,9 @@ module main;
wire clk_sys; wire clk_sys;
wire rst_n; wire rst_n;
wire clk_sys_dly; //wire clk_sys_dly;
wire time_valid; reg [39:0] tm_seconds=1;
reg [27:0] tm_cycles=0;
IWishboneMaster WB ( IWishboneMaster WB (
.clk_i(clk_sys), .clk_i(clk_sys),
...@@ -27,50 +28,61 @@ module main; ...@@ -27,50 +28,61 @@ module main;
.rst_n_o(rst_n)); .rst_n_o(rst_n));
assign #10 clk_sys_dly = clk_sys; //assign #10 clk_sys_dly = clk_sys;
assign #1 time_valid =1'b1; //assign #10ns time_valid =1'b1;
wrsw_dio wrsw_dio
#( #(
.g_interface_mode(PIPELINED), .g_interface_mode(PIPELINED),
.g_address_granularity(BYTE)) .g_address_granularity(WORD))
DUT( DUT(
.clk_sys_i (clk_sys), .clk_sys_i (clk_sys),
.clk_ref_i (clk_ref), .clk_ref_i (clk_ref),
.rst_n_i (rst_n), .rst_n_i (rst_n),
.tm_time_valid_i(time_valid), .tm_time_valid_i(1'b1),
.tm_seconds_i(tm_seconds),
.wb_cyc_i (WB.master.cyc), .tm_cycles_i(tm_cycles),
.wb_stb_i (WB.master.stb),
.wb_we_i (WB.master.we), .wb_adr_i (WB.master.adr[31:0]),
.wb_sel_i (4'b1111), .wb_dat_i (WB.master.dat_o),
.wb_adr_i (WB.master.adr[31:0]), .wb_dat_o (WB.master.dat_i),
.wb_dat_i (WB.master.dat_o), .wb_sel_i (4'b1111),
.wb_dat_o (WB.master.dat_i), .wb_we_i (WB.master.we),
.wb_ack_o (WB.master.ack), .wb_cyc_i (WB.master.cyc),
.wb_stall_o(WB.master.stall) .wb_stb_i (WB.master.stb),
.wb_ack_o (WB.master.ack),
.wb_stall_o (WB.master.stall)
); );
always @(posedge clk_ref) begin
tm_cycles++;
if (tm_cycles==0)
tm_seconds++;
end;
initial begin initial begin
CWishboneAccessor acc; CWishboneAccessor acc;
uint64_t data; uint64_t data;
@(posedge rst_n); @(posedge rst_n);
repeat(3) @(posedge clk_sys); repeat(3) @(posedge clk_sys);
#1us;
acc = WB.get_accessor(); #1us;
acc = WB.get_accessor();
acc.set_mode(PIPELINED); acc.set_mode(PIPELINED);
#1us;
acc.write(32'h00000000, 'h11111111);
#1us; #40ns
acc.write(32'h00000000, 'hdeadbeef); acc.read (32'h00000000, data);
//acc.write(32'h00008000, 'hdeadbeef);
//acc.write(32'h00008000, 'hdeadbeef);
//#1us; //#1us;
acc.write(32'h00000004, 'hcafebabe); //acc.write(32'h00000004, 'hcafebabe);
//acc.write(32'h00008004, 'hcafebabe); //acc.write(32'h00008004, 'hcafebabe);
/* acc.read(32'h00000000, data); /* acc.read(32'h00000000, data);
......
testbench/wrsw_dio/wave.do
View file @ 87566221
...@@ -3,7 +3,7 @@ quietly WaveActivateNextPane {} 0 ...@@ -3,7 +3,7 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_sys_i add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/clk_ref_i add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/rst_n_i add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/tm_time_valid_i
add wave -divider WB add wave -divider WB
add wave -noupdate /main/DUT/wb_cyc_i add wave -noupdate /main/DUT/wb_cyc_i
...@@ -16,6 +16,10 @@ add wave -noupdate /main/DUT/wb_dat_o ...@@ -16,6 +16,10 @@ add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_ack_o add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_stall_o add wave -noupdate /main/DUT/wb_stall_o
add wave -divider wr-core_time_input
add wave -noupdate /main/DUT/tm_time_valid_i
add wave -noupdate /main/DUT/tm_seconds_i
add wave -noupdate /main/DUT/tm_cycles_i
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0} WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
......
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