pipelined wb slaves and dio adapter

87566221 · Javier Díaz · Miguel Jimenez Lopez · fa62367d · 87566221 · 87566221
Commit 87566221 authored Jul 29, 2012 by Javier Díaz Committed by Miguel Jimenez Lopez Apr 03, 2019
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Showing with 41 additions and 25 deletions

main.sv testbench/wrsw_dio/main.sv +36 -24

wave.do testbench/wrsw_dio/wave.do +5 -1

No files found.
--- a/testbench/wrsw_dio/main.sv
+++ b/testbench/wrsw_dio/main.sv
@@ -11,8 +11,9 @@ module main;
   wire clk_sys;
   wire rst_n;

-   wire clk_sys_dly;
-   wire time_valid;
+   //wire clk_sys_dly;
+   reg [39:0] tm_seconds=1;
+   reg [27:0] tm_cycles=0;

   IWishboneMaster WB (
      .clk_i(clk_sys),
@@ -27,31 +28,38 @@ module main;
 	.rst_n_o(rst_n));


-   assign  #10 clk_sys_dly  = clk_sys;
-   assign  #1  time_valid =1'b1;
+   //assign  #10 clk_sys_dly  = clk_sys;
+   //assign  #10ns  time_valid =1'b1;
  
   wrsw_dio 
      #(
        .g_interface_mode(PIPELINED),
-        .g_address_granularity(BYTE)) 
+        .g_address_granularity(WORD)) 
    DUT(
      .clk_sys_i (clk_sys),
      .clk_ref_i (clk_ref),
      .rst_n_i   (rst_n),

-      .tm_time_valid_i(time_valid),
+      .tm_time_valid_i(1'b1),
+      .tm_seconds_i(tm_seconds),
+      .tm_cycles_i(tm_cycles),

-      .wb_cyc_i  (WB.master.cyc),
-      .wb_stb_i  (WB.master.stb),
-      .wb_we_i   (WB.master.we),
-      .wb_sel_i  (4'b1111),
 	.wb_adr_i      (WB.master.adr[31:0]),
 	.wb_dat_i      (WB.master.dat_o),
 	.wb_dat_o      (WB.master.dat_i),
+	.wb_sel_i       (4'b1111),
+	.wb_we_i        (WB.master.we),
+	.wb_cyc_i       (WB.master.cyc),
+	.wb_stb_i       (WB.master.stb),
 	.wb_ack_o       (WB.master.ack),
-      .wb_stall_o(WB.master.stall)
+        .wb_stall_o     (WB.master.stall)
    );

+   always @(posedge clk_ref) begin
+     tm_cycles++;
+     if  (tm_cycles==0)
+       tm_seconds++;
+   end;
   
   initial begin
      CWishboneAccessor acc;
@@ -61,16 +69,20 @@ module main;
      repeat(3) @(posedge clk_sys);
            
      #1us;            
-            
      acc  = WB.get_accessor();      
      acc.set_mode(PIPELINED);

      #1us;
-      acc.write(32'h00000000, 'hdeadbeef);
-      //acc.write(32'h00008000, 'hdeadbeef);
+
+      acc.write(32'h00000000, 'h11111111);
+      
+      #40ns
+      acc.read (32'h00000000, data);      
+
+//acc.write(32'h00008000, 'hdeadbeef);

      //#1us;
-      acc.write(32'h00000004, 'hcafebabe);
+      //acc.write(32'h00000004, 'hcafebabe);
      //acc.write(32'h00008004, 'hcafebabe);

 /*     acc.read(32'h00000000, data);

--- a/testbench/wrsw_dio/wave.do
+++ b/testbench/wrsw_dio/wave.do
@@ -3,7 +3,7 @@ quietly WaveActivateNextPane {} 0
 add wave -noupdate /main/DUT/clk_sys_i
 add wave -noupdate /main/DUT/clk_ref_i
 add wave -noupdate /main/DUT/rst_n_i
-add wave -noupdate /main/DUT/tm_time_valid_i
+

 add wave -divider WB
 add wave -noupdate /main/DUT/wb_cyc_i
@@ -16,6 +16,10 @@ add wave -noupdate /main/DUT/wb_dat_o
 add wave -noupdate /main/DUT/wb_ack_o
 add wave -noupdate /main/DUT/wb_stall_o

+add wave -divider wr-core_time_input
+add wave -noupdate /main/DUT/tm_time_valid_i
+add wave -noupdate /main/DUT/tm_seconds_i
+add wave -noupdate /main/DUT/tm_cycles_i

 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}