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FMC DIO 5ch TTL a
Commit a414b20d authored by Rafael Rodriguez's avatar Rafael Rodriguez Committed by Miguel Jimenez Lopez
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adding fifo_regs and dummy_time module in wrsw_dio

parent 77c798b6
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modules/wrsw_dio/Manifest.py 0 → 100644
View file @ a414b20d
files = ["wrsw_dio_wb.vhd",
"wrsw_dio.vhd",
"dummy_time.vhd",
"wrsw_dio.wb",
"wrsw_dio_wb.htm"]
modules/wrsw_dio/dummy_time.vhd 0 → 100755
View file @ a414b20d
-------------------------------------------------------------------------------
-- Entity: dummy_time
-- File: dummy_time.vhd
-- Description: ¿?
-- Author: Javier Diaz (jdiaz@atc.ugr.es)
-- Date: 8 March 2012
-- Version: 0.01
-- To do:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- -----------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details. You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it from
-- http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity dummy_time is
port(clk_sys : in std_logic; -- data output reference clock 125MHz
rst_n: in std_logic; -- system reset
-- utc time in seconds
tm_utc : out std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles : out std_logic_vector(27 downto 0));
end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
begin
---------------------------------------
-- Process to count cycles in a second
---------------------------------------
P_CountTM_cycles:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
oneSecond <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
else
tm_cycles_Aux <= (others=>'0');
end if;
if(Tm_cycles_Aux = MaxCountcycles1) then
OneSecond <= '1';
else
OneSecond <= '0';
end if;
end if;
end process P_CountTM_cycles;
P_CountTM_UTC:
process(rst_n, clk_sys)
begin
if(rst_n = '0') then
tm_utc_Aux <= (others=>'0');
elsif(rising_edge(Clk_sys)) then
if (OneSecond='1') then
if (tm_utc_Aux /= AllOnesUTC) then
tm_utc_Aux <= tm_utc_Aux + 1;
else
tm_utc_Aux <= (others=>'0');
end if;
end if;
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux;
tm_utc <= tm_utc_Aux;
end Behavioral;
modules/wrsw_dio/wrsw_dio.vhd
View file @ a414b20d
......@@ -40,14 +40,12 @@ entity wrsw_dio is
);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_clk_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
......@@ -138,33 +136,6 @@ architecture rtl of wrsw_dio is
begin -- rtl
gen_dio_iobufs : for i in 0 to 4 generate
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i)
);
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
U_input_buffer : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_clk,
I => dio_clk_p_i,
IB => dio_clk_n_i
);
U_Onewire : xwb_onewire_master
generic map (
g_interface_mode => CLASSIC,
......
modules/wrsw_dio/wrsw_dio.wb
View file @ a414b20d
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
......@@ -69,4 +71,4 @@ peripheral {
trigger = LEVEL_1;
};
};
\ No newline at end of file
};
modules/wrsw_dio/wrsw_dio_wb.htm 0 → 100755
View file @ a414b20d
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modules/wrsw_dio/wrsw_dio_wb.vhd 0 → 100755
View file @ a414b20d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC-DIO-5chttla
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Sun Mar 11 01:37:23 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wrsw_dio_wb is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_utc_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_utch_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trig0_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 0 UTC-based trigger for pulse generation'
dio_trigh0_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trig1_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 1 UTC-based trigger for pulse generation'
dio_trigh1_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trig2_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 2 UTC-based trigger for pulse generation'
dio_trigh2_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trig3_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 3 UTC-based trigger for pulse generation'
dio_trigh3_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trig4_utc_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'utc field' in reg: 'fmc-dio 4 UTC-based trigger for pulse generation'
dio_trigh4_utc_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'trig_enable field' in reg: 'FMC-DIO UTC-based trigger Enable-register for pulse generation'
dio_trig_ena_ena_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO UTC-based trigger ready informaton for pulse generation'
dio_trig_ena_rdy_i : in std_logic_vector(4 downto 0)
);
end wrsw_dio_wb;
architecture syn of wrsw_dio_wb is
signal dio_tsf0_in_int : std_logic_vector(67 downto 0);
signal dio_tsf0_out_int : std_logic_vector(67 downto 0);
signal dio_tsf0_rdreq_int : std_logic ;
signal dio_tsf0_rdreq_int_d0 : std_logic ;
signal dio_tsf1_in_int : std_logic_vector(67 downto 0);
signal dio_tsf1_out_int : std_logic_vector(67 downto 0);
signal dio_tsf1_rdreq_int : std_logic ;
signal dio_tsf1_rdreq_int_d0 : std_logic ;
signal dio_tsf2_in_int : std_logic_vector(67 downto 0);
signal dio_tsf2_out_int : std_logic_vector(67 downto 0);
signal dio_tsf2_rdreq_int : std_logic ;
signal dio_tsf2_rdreq_int_d0 : std_logic ;
signal dio_tsf3_in_int : std_logic_vector(67 downto 0);
signal dio_tsf3_out_int : std_logic_vector(67 downto 0);
signal dio_tsf3_rdreq_int : std_logic ;
signal dio_tsf3_rdreq_int_d0 : std_logic ;
signal dio_tsf4_in_int : std_logic_vector(67 downto 0);
signal dio_tsf4_out_int : std_logic_vector(67 downto 0);
signal dio_tsf4_rdreq_int : std_logic ;
signal dio_tsf4_rdreq_int_d0 : std_logic ;
signal dio_trig0_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh0_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig1_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh1_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig2_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh2_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig3_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh3_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_utc_int : std_logic_vector(31 downto 0);
signal dio_trigh4_utc_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig_ena_ena_int : std_logic_vector(4 downto 0);
signal eic_idr_int : std_logic_vector(4 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(4 downto 0);
signal eic_isr_clear_int : std_logic_vector(4 downto 0);
signal eic_isr_status_int : std_logic_vector(4 downto 0);
signal eic_irq_ack_int : std_logic_vector(4 downto 0);
signal eic_isr_write_int : std_logic ;
signal dio_tsf0_full_int : std_logic ;
signal dio_tsf0_empty_int : std_logic ;
signal dio_tsf0_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf1_full_int : std_logic ;
signal dio_tsf1_empty_int : std_logic ;
signal dio_tsf1_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf2_full_int : std_logic ;
signal dio_tsf2_empty_int : std_logic ;
signal dio_tsf2_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf3_full_int : std_logic ;
signal dio_tsf3_empty_int : std_logic ;
signal dio_tsf3_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int : std_logic ;
signal dio_tsf4_empty_int : std_logic ;
signal dio_tsf4_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(4 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dio_trig0_utc_int <= "00000000000000000000000000000000";
dio_trigh0_utc_int <= "00000000";
dio_cyc0_cyc_int <= "0000000000000000000000000000";
dio_trig1_utc_int <= "00000000000000000000000000000000";
dio_trigh1_utc_int <= "00000000";
dio_cyc1_cyc_int <= "0000000000000000000000000000";
dio_trig2_utc_int <= "00000000000000000000000000000000";
dio_trigh2_utc_int <= "00000000";
dio_cyc2_cyc_int <= "0000000000000000000000000000";
dio_trig3_utc_int <= "00000000000000000000000000000000";
dio_trigh3_utc_int <= "00000000";
dio_cyc3_cyc_int <= "0000000000000000000000000000";
dio_trig4_utc_int <= "00000000000000000000000000000000";
dio_trigh4_utc_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_trig_ena_ena_int <= "00000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
dio_tsf0_rdreq_int <= '0';
dio_tsf1_rdreq_int <= '0';
dio_tsf2_rdreq_int <= '0';
dio_tsf3_rdreq_int <= '0';
dio_tsf4_rdreq_int <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
dio_trig0_utc_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dio_trig0_utc_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
dio_trigh0_utc_int <= wrdata_reg(7 downto 0);
else
rddata_reg(7 downto 0) <= dio_trigh0_utc_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
dio_cyc0_cyc_int <= wrdata_reg(27 downto 0);
else
rddata_reg(27 downto 0) <= dio_cyc0_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
dio_trig1_utc_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dio_trig1_utc_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
dio_trigh1_utc_int <= wrdata_reg(7 downto 0);
else
rddata_reg(7 downto 0) <= dio_trigh1_utc_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
dio_cyc1_cyc_int <= wrdata_reg(27 downto 0);
else
rddata_reg(27 downto 0) <= dio_cyc1_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
dio_trig2_utc_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dio_trig2_utc_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
dio_trigh2_utc_int <= wrdata_reg(7 downto 0);
else
rddata_reg(7 downto 0) <= dio_trigh2_utc_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
dio_cyc2_cyc_int <= wrdata_reg(27 downto 0);
else
rddata_reg(27 downto 0) <= dio_cyc2_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
dio_trig3_utc_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dio_trig3_utc_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
dio_trigh3_utc_int <= wrdata_reg(7 downto 0);
else
rddata_reg(7 downto 0) <= dio_trigh3_utc_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
dio_cyc3_cyc_int <= wrdata_reg(27 downto 0);
else
rddata_reg(27 downto 0) <= dio_cyc3_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
dio_trig4_utc_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dio_trig4_utc_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
dio_trigh4_utc_int <= wrdata_reg(7 downto 0);
else
rddata_reg(7 downto 0) <= dio_trigh4_utc_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
if (wb_we_i = '1') then
dio_cyc4_cyc_int <= wrdata_reg(27 downto 0);
else
rddata_reg(27 downto 0) <= dio_cyc4_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
dio_trig_ena_ena_int <= wrdata_reg(4 downto 0);
else
rddata_reg(4 downto 0) <= dio_trig_ena_ena_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
else
rddata_reg(4 downto 0) <= dio_trig_ena_rdy_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
else
rddata_reg(4 downto 0) <= eic_imr_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
rddata_reg(4 downto 0) <= eic_isr_status_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
else
if (dio_tsf0_rdreq_int_d0 = '0') then
dio_tsf0_rdreq_int <= not dio_tsf0_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf0_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
end if;
when "011101" =>
if (wb_we_i = '1') then
else
rddata_reg(7 downto 0) <= dio_tsf0_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= dio_tsf0_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
else
rddata_reg(16) <= dio_tsf0_full_int;
rddata_reg(17) <= dio_tsf0_empty_int;
rddata_reg(7 downto 0) <= dio_tsf0_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
else
if (dio_tsf1_rdreq_int_d0 = '0') then
dio_tsf1_rdreq_int <= not dio_tsf1_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf1_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
end if;
when "100001" =>
if (wb_we_i = '1') then
else
rddata_reg(7 downto 0) <= dio_tsf1_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= dio_tsf1_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
else
rddata_reg(16) <= dio_tsf1_full_int;
rddata_reg(17) <= dio_tsf1_empty_int;
rddata_reg(7 downto 0) <= dio_tsf1_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
else
if (dio_tsf2_rdreq_int_d0 = '0') then
dio_tsf2_rdreq_int <= not dio_tsf2_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf2_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
end if;
when "100101" =>
if (wb_we_i = '1') then
else
rddata_reg(7 downto 0) <= dio_tsf2_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= dio_tsf2_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
else
rddata_reg(16) <= dio_tsf2_full_int;
rddata_reg(17) <= dio_tsf2_empty_int;
rddata_reg(7 downto 0) <= dio_tsf2_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
else
if (dio_tsf3_rdreq_int_d0 = '0') then
dio_tsf3_rdreq_int <= not dio_tsf3_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf3_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
end if;
when "101001" =>
if (wb_we_i = '1') then
else
rddata_reg(7 downto 0) <= dio_tsf3_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= dio_tsf3_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
if (wb_we_i = '1') then
else
rddata_reg(16) <= dio_tsf3_full_int;
rddata_reg(17) <= dio_tsf3_empty_int;
rddata_reg(7 downto 0) <= dio_tsf3_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
if (wb_we_i = '1') then
else
if (dio_tsf4_rdreq_int_d0 = '0') then
dio_tsf4_rdreq_int <= not dio_tsf4_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf4_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
end if;
when "101101" =>
if (wb_we_i = '1') then
else
rddata_reg(7 downto 0) <= dio_tsf4_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101110" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= dio_tsf4_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101111" =>
if (wb_we_i = '1') then
else
rddata_reg(16) <= dio_tsf4_full_int;
rddata_reg(17) <= dio_tsf4_empty_int;
rddata_reg(7 downto 0) <= dio_tsf4_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO 0
dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_utc_i;
dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_utch_i;
dio_tsf0_in_int(67 downto 40) <= dio_tsf0_tag_cycles_i;
dio_tsf0_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf0_wr_req_i,
wr_full_o => dio_tsf0_wr_full_o,
wr_empty_o => dio_tsf0_wr_empty_o,
rd_full_o => dio_tsf0_full_int,
rd_empty_o => dio_tsf0_empty_int,
rd_usedw_o => dio_tsf0_usedw_int,
rd_req_i => dio_tsf0_rdreq_int,
clk_i => bus_clock_int,
wr_data_i => dio_tsf0_in_int,
rd_data_o => dio_tsf0_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 1
dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_utc_i;
dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_utch_i;
dio_tsf1_in_int(67 downto 40) <= dio_tsf1_tag_cycles_i;
dio_tsf1_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf1_wr_req_i,
wr_full_o => dio_tsf1_wr_full_o,
wr_empty_o => dio_tsf1_wr_empty_o,
rd_full_o => dio_tsf1_full_int,
rd_empty_o => dio_tsf1_empty_int,
rd_usedw_o => dio_tsf1_usedw_int,
rd_req_i => dio_tsf1_rdreq_int,
clk_i => bus_clock_int,
wr_data_i => dio_tsf1_in_int,
rd_data_o => dio_tsf1_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 2
dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_utc_i;
dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_utch_i;
dio_tsf2_in_int(67 downto 40) <= dio_tsf2_tag_cycles_i;
dio_tsf2_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf2_wr_req_i,
wr_full_o => dio_tsf2_wr_full_o,
wr_empty_o => dio_tsf2_wr_empty_o,
rd_full_o => dio_tsf2_full_int,
rd_empty_o => dio_tsf2_empty_int,
rd_usedw_o => dio_tsf2_usedw_int,
rd_req_i => dio_tsf2_rdreq_int,
clk_i => bus_clock_int,
wr_data_i => dio_tsf2_in_int,
rd_data_o => dio_tsf2_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 3
dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_utc_i;
dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_utch_i;
dio_tsf3_in_int(67 downto 40) <= dio_tsf3_tag_cycles_i;
dio_tsf3_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf3_wr_req_i,
wr_full_o => dio_tsf3_wr_full_o,
wr_empty_o => dio_tsf3_wr_empty_o,
rd_full_o => dio_tsf3_full_int,
rd_empty_o => dio_tsf3_empty_int,
rd_usedw_o => dio_tsf3_usedw_int,
rd_req_i => dio_tsf3_rdreq_int,
clk_i => bus_clock_int,
wr_data_i => dio_tsf3_in_int,
rd_data_o => dio_tsf3_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 4
dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_utc_i;
dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_utch_i;
dio_tsf4_in_int(67 downto 40) <= dio_tsf4_tag_cycles_i;
dio_tsf4_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf4_wr_req_i,
wr_full_o => dio_tsf4_wr_full_o,
wr_empty_o => dio_tsf4_wr_empty_o,
rd_full_o => dio_tsf4_full_int,
rd_empty_o => dio_tsf4_empty_int,
rd_usedw_o => dio_tsf4_usedw_int,
rd_req_i => dio_tsf4_rdreq_int,
clk_i => bus_clock_int,
wr_data_i => dio_tsf4_in_int,
rd_data_o => dio_tsf4_out_int
);
-- utc field
dio_trig0_utc_o <= dio_trig0_utc_int;
-- utc field
dio_trigh0_utc_o <= dio_trigh0_utc_int;
-- cycles field
dio_cyc0_cyc_o <= dio_cyc0_cyc_int;
-- utc field
dio_trig1_utc_o <= dio_trig1_utc_int;
-- utc field
dio_trigh1_utc_o <= dio_trigh1_utc_int;
-- cycles field
dio_cyc1_cyc_o <= dio_cyc1_cyc_int;
-- utc field
dio_trig2_utc_o <= dio_trig2_utc_int;
-- utc field
dio_trigh2_utc_o <= dio_trigh2_utc_int;
-- cycles field
dio_cyc2_cyc_o <= dio_cyc2_cyc_int;
-- utc field
dio_trig3_utc_o <= dio_trig3_utc_int;
-- utc field
dio_trigh3_utc_o <= dio_trigh3_utc_int;
-- cycles field
dio_cyc3_cyc_o <= dio_cyc3_cyc_int;
-- utc field
dio_trig4_utc_o <= dio_trig4_utc_int;
-- utc field
dio_trigh4_utc_o <= dio_trigh4_utc_int;
-- cycles field
dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- trig_enable field
dio_trig_ena_ena_o <= dio_trig_ena_ena_int;
-- trig_rdy field
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 5,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 3,
g_irq04_mode => 3,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => bus_clock_int,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_irq_o
);
irq_inputs_vector_int(0) <= irq_nempty_0_i;
irq_inputs_vector_int(1) <= irq_nempty_1_i;
irq_inputs_vector_int(2) <= irq_nempty_2_i;
irq_inputs_vector_int(3) <= irq_nempty_3_i;
irq_inputs_vector_int(4) <= irq_nempty_4_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 0
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf0_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
dio_tsf0_rdreq_int_d0 <= dio_tsf0_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 0
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf1_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
dio_tsf1_rdreq_int_d0 <= dio_tsf1_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 0
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf2_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
dio_tsf2_rdreq_int_d0 <= dio_tsf2_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 0
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf3_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
dio_tsf3_rdreq_int_d0 <= dio_tsf3_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 0
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf4_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
dio_tsf4_rdreq_int_d0 <= dio_tsf4_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 2
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
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