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FMC DIO 5ch TTL a
Commit ae17ac52 authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez
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Synchronize PPS signals from clk_ref (125 MHz) to clk_sys (62.5 MHz).

parent 34b0830c
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Showing with 56 additions and 9 deletions
hdl/top/dio-common/dio_common_top.vhd
View file @ ae17ac52
......@@ -299,8 +299,10 @@ architecture top of dio_common_top is
attribute IOB of wrc_pps_out: signal is "TRUE";
signal wrc_pps_csync_out : std_logic;
signal wrc_pps_csync_out_ext : std_logic;
signal wrc_pps_csync_out_ext_int : std_logic;
signal wrc_pps_valid_out : std_logic;
signal wrc_pps_valid_out_ext : std_logic;
signal wrc_pps_valid_out_ext_int : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
......@@ -532,8 +534,19 @@ begin -- architecture top
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_csync_out,
extended_o => wrc_pps_csync_out_ext);
extended_o => wrc_pps_csync_out_ext_int);
sync_ffs_pps_csync : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
data_i => wrc_pps_csync_out_ext_int,
synced_o => open,
npulse_o => open,
ppulse_o => wrc_pps_csync_out_ext);
-- Logic to extend pps_valid_o (125 MHz) in order to be detected
-- in clk_sys (62.5 MHz) domain.
U_Extend_pps_valid : gc_extend_pulse
......@@ -543,7 +556,18 @@ begin -- architecture top
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_valid_out,
extended_o => wrc_pps_valid_out_ext);
extended_o => wrc_pps_valid_out_ext_int);
sync_ffs_pps_valid : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
data_i => wrc_pps_valid_out_ext_int,
synced_o => open,
npulse_o => open,
ppulse_o => wrc_pps_valid_out_ext);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
......
hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
View file @ ae17ac52
......@@ -3,7 +3,7 @@
-- Project : FMC DIO 5CH TTa
-------------------------------------------------------------------------------
-- File : dio_ext_nic_etherbone.vhd
-- Author : Grzegorz Daniluk, Rafael Rodriguez, Javier Díaz, Miguel Jimenez
-- Author : Grzegorz Daniluk, Rafael Rodriguez, Javier Daz, Miguel Jimenez
-- Company : Elproma, Seven Solutions, UGR
-- Created : 2012-02-08
-- Last update: 2019-03-27
......@@ -14,7 +14,7 @@
-- This design contains the old configuration for the WR-NIC project with DIO,
-- Etherbone and NIC capabilities.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk, Rafael Rodriguez, Javier Díaz
-- Copyright (c) 2012 Grzegorz Daniluk, Rafael Rodriguez, Javier Daz
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
......@@ -282,7 +282,7 @@ architecture top of dio_ext_nic_etherbone_top is
-- Constants
-----------------------------------------------------------------------------
-- Number of interrupts
constant c_NUM_IRQS : integer := 3;
constant c_NUM_IRQS : integer := 4;
-- Interrupts IDs
constant c_IRQ_TXTSU : integer := 0;
......@@ -382,11 +382,13 @@ architecture top of dio_ext_nic_etherbone_top is
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_csync_out_ext_int : std_logic;
signal wrc_pps_csync_out_ext : std_logic;
attribute IOB: string;
attribute IOB of wrc_pps_out: signal is "TRUE";
signal wrc_pps_csync : std_logic;
signal wrc_pps_valid : std_logic;
signal wrc_pps_valid_out_ext_int : std_logic;
signal wrc_pps_valid_out_ext : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
......@@ -403,7 +405,7 @@ architecture top of dio_ext_nic_etherbone_top is
-- VIC
signal vic_irq : std_logic;
signal vic_slave_irq : std_logic_vector(2 downto 0);
signal vic_slave_irq : std_logic_vector(c_NUM_IRQS-1 downto 0);
-- TxTSU
signal txtsu_timestamps : t_txtsu_timestamp;
......@@ -432,7 +434,6 @@ architecture top of dio_ext_nic_etherbone_top is
signal dio_int : std_logic;
begin -- architecture top
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar (With GN4124 and Etherbone as Masters)
-----------------------------------------------------------------------------
......@@ -659,7 +660,18 @@ begin -- architecture top
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_csync,
extended_o => wrc_pps_csync_out_ext);
extended_o => wrc_pps_csync_out_ext_int);
sync_ffs_pps_csync : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
data_i => wrc_pps_csync_out_ext_int,
synced_o => open,
npulse_o => open,
ppulse_o => wrc_pps_csync_out_ext);
-- Logic to extend pps_valid_o (125 MHz) in order to be detected
-- in clk_sys (62.5 MHz) domain.
......@@ -670,7 +682,18 @@ begin -- architecture top
clk_i => clk_ref_125m,
rst_n_i => rst_ref_125m_n,
pulse_i => wrc_pps_valid,
extended_o => wrc_pps_valid_out_ext);
extended_o => wrc_pps_valid_out_ext_int);
sync_ffs_pps_valid : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
data_i => wrc_pps_valid_out_ext_int,
synced_o => open,
npulse_o => open,
ppulse_o => wrc_pps_valid_out_ext);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
......
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