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FMC DIO 5ch TTL a
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FMC DIO 5ch TTL a
Commits
b19d8b3e
Commit
b19d8b3e
authored
Mar 15, 2012
by
Rafael Rodriguez
Committed by
Miguel Jimenez Lopez
Apr 03, 2019
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new memory map
parent
a61907bf
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1 changed file
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10 additions
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10 deletions
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wrsw_dio.vhd
modules/wrsw_dio/wrsw_dio.vhd
+10
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modules/wrsw_dio/wrsw_dio.vhd
View file @
b19d8b3e
...
...
@@ -311,16 +311,16 @@ end component;
-- WB Crossbar
-------------------
constant
c_cfg_base_addr
:
t_wishbone_address_array
(
3
downto
0
)
:
=
(
0
=>
x"000
0
0000"
,
-- ONEWIRE
1
=>
x"000
0004
0"
,
-- I2C
2
=>
x"000
0008
0"
,
-- GPIO
3
=>
x"000
000C
0"
);
-- PULSE GEN & STAMPER
(
0
=>
x"000
6
0000"
,
-- ONEWIRE
1
=>
x"000
6010
0"
,
-- I2C
2
=>
x"000
6020
0"
,
-- GPIO
3
=>
x"000
6030
0"
);
-- PULSE GEN & STAMPER
constant
c_cfg_base_mask
:
t_wishbone_address_array
(
3
downto
0
)
:
=
(
0
=>
x"ffffff
c
0"
,
1
=>
x"ffffff
c
0"
,
2
=>
x"ffffff
c
0"
,
3
=>
x"ffffff
c
0"
);
(
0
=>
x"ffffff
0
0"
,
1
=>
x"ffffff
0
0"
,
2
=>
x"ffffff
0
0"
,
3
=>
x"ffffff
0
0"
);
signal
cbar_master_in
:
t_wishbone_master_in_array
(
c_WB_SLAVES_DIO
-1
downto
0
);
...
...
@@ -514,7 +514,7 @@ begin
wb_we_i
=>
cbar_master_out
(
3
)
.
we
,
wb_ack_o
=>
cbar_master_in
(
3
)
.
ack
,
wb_stall_o
=>
cbar_master_in
(
3
)
.
stall
,
wb_int_o
=>
slave_o
.
int
,
wb_int_o
=>
wb_irq_data_fifo_o
,
--
slave_o.int,
dio_tsf0_wr_req_i
=>
dio_tsf_wr_req
(
0
),
dio_tsf0_wr_full_o
=>
dio_tsf_wr_full
(
0
),
...
...
@@ -581,7 +581,7 @@ begin
);
--interrupt from fifos
wb_irq_data_fifo_o
<=
cbar_master_in
(
3
)
.
int
;
--
wb_irq_data_fifo_o <= cbar_master_in(3).int;
-----------------------------------------------------------------------------------
------ signals for debugging
...
...
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