Commit b5f355ed authored by Maciej Lipinski's avatar Maciej Lipinski

Merge branch 'klyone-20190412-fix_copyright_licenses' into 'master'

Klyone 20190412 fix copyright licenses

See merge request !2
parents c917e02c 033ff03d
Subproject commit 4e5e3dfc01e395a81d9403bd1e150560972685f7 Subproject commit 3a0e82cabaed8e7d738b09be03981e38d66ea1b6
...@@ -6,14 +6,31 @@ ...@@ -6,14 +6,31 @@
-- Author : Javier Díaz -- Author : Javier Díaz
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2012-07-25 -- Created : 2012-07-25
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Simulation file for the xwr_dio.vhd file -- Description: Simulation file for the xwr_dio.vhd file
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- TODO: -- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Javier Díaz -- Author : Javier Díaz
-- Company : Seven Solutions, UGR -- Company : Seven Solutions, UGR
-- Created : 2012-07-18 -- Created : 2012-07-18
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -14,7 +14,24 @@ ...@@ -14,7 +14,24 @@
-- Standard data bus (SDB) definitions for White Rabbit Network Interface Card (WR NIC= -- Standard data bus (SDB) definitions for White Rabbit Network Interface Card (WR NIC=
-- # -- #
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2012 Javier Díaz -- Copyright (c) 2012 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Rafael Rodriguez, Javier Daz -- Author : Rafael Rodriguez, Javier Daz
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2012-03-03 -- Created : 2012-03-03
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -17,7 +17,24 @@ ...@@ -17,7 +17,24 @@
-- to schedule the generation of a pulse at a given future seconds time, or to generate -- to schedule the generation of a pulse at a given future seconds time, or to generate
-- it immediately. -- it immediately.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- TODO: Include wb adapter -- Copyright 2019, CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,14 +6,31 @@ ...@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez -- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2019-03-27 -- Created : 2019-03-27
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- DIO design with NIC or Etherbone capabilities. -- DIO design with NIC or Etherbone capabilities.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions -- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,14 +6,31 @@ ...@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez -- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2019-03-27 -- Created : 2019-03-27
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- DIO common package with NIC or Etherbone capabilities. -- DIO common package with NIC or Etherbone capabilities.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions -- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,14 +6,31 @@ ...@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez -- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2019-03-27 -- Created : 2019-03-27
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- DIO design with Etherbone capabilities. -- DIO design with Etherbone capabilities.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions -- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk, Rafael Rodriguez, Javier Daz, Miguel Jimenez -- Author : Grzegorz Daniluk, Rafael Rodriguez, Javier Daz, Miguel Jimenez
-- Company : Elproma, Seven Solutions, UGR -- Company : Elproma, Seven Solutions, UGR
-- Created : 2012-02-08 -- Created : 2012-02-08
-- Last update: 2019-08-28 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -18,7 +18,24 @@ ...@@ -18,7 +18,24 @@
-- to wr-nic-v2.1 design. It remains in the git repository for historical and -- to wr-nic-v2.1 design. It remains in the git repository for historical and
-- traceability reasons. -- traceability reasons.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk, Rafael Rodriguez, Javier Daz -- Copyright (c) 2012 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -6,14 +6,31 @@ ...@@ -6,14 +6,31 @@
-- Author : Miguel Jimenez-Lopez -- Author : Miguel Jimenez-Lopez
-- Company : Seven Solutions -- Company : Seven Solutions
-- Created : 2019-03-27 -- Created : 2019-03-27
-- Last update: 2019-08-27 -- Last update: 2019-12-04
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- DIO design with NIC capabilities. -- DIO design with NIC capabilities.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2019 Seven Solutions -- Copyright (c) 2019 CERN (www.cern.ch)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
/* /*
* Copyright (C) 2019 CERN (www.sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
......
/* /*
* Copyright (C) 2019 CERN (www.sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
......
/* /*
* Copyright (C) 2019 CERN (www.sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
......
/* /*
* Copyright (C) 2019 Seven Solutions (www.sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
*
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* Author: Alessandro Rubini <rubini@gnudd.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
* *
......
/* /*
* Copyright (C) 2019 CERN (www.sevensols.com) * Copyright (C) 2019 CERN (www.cern.ch)
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
* Released according to the GNU GPL, version 2 or any later version. * Released according to the GNU GPL, version 2 or any later version.
......
/* /*
* Copyright (C) 2012 CERN (www.cern.ch) * Copyright (C) 2012 CERN (www.cern.ch)
* Copyright (C) 2019 Seven Solutions (sevensols.com) *
* Author: Alessandro Rubini <rubini@gnudd.com> * Author: Alessandro Rubini <rubini@gnudd.com>
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
......
/* /*
* Copyright (C) 2012 CERN (www.cern.ch) * Copyright (C) 2012 CERN (www.cern.ch)
* Copyright (C) 2019 Seven Solutions (sevensols.com) *
* Author: Alessandro Rubini <rubini@gnudd.com> * Author: Alessandro Rubini <rubini@gnudd.com>
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
......
/* /*
* Copyright (C) 2012 CERN (www.cern.ch) * Copyright (C) 2012 CERN (www.cern.ch)
* Copyright (C) 2019 Seven Solutions (sevensols.com) *
* Author: Alessandro Rubini <rubini@gnudd.com> * Author: Alessandro Rubini <rubini@gnudd.com>
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
......
/* /*
* Copyright (C) 2012 CERN (www.cern.ch) * Copyright (C) 2012 CERN (www.cern.ch)
* Copyright (C) 2019 Seven Solutions (sevensols.com) *
* Author: Alessandro Rubini <rubini@gnudd.com> * Author: Alessandro Rubini <rubini@gnudd.com>
* Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com> * Author: Miguel Jimenez Lopez <miguel.jimenez@sevensols.com>
* *
......
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