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FMC DIO 5ch TTL a
Commit c2e58275 authored by Rafael Rodriguez's avatar Rafael Rodriguez Committed by Miguel Jimenez Lopez
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removed comments in top file

parent d3981255
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Showing with 173 additions and 171 deletions
modules/wrsw_dio/dummy_time.vhd
View file @ c2e58275
......@@ -24,7 +24,6 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.NUMERIC_STD.ALL;
......@@ -42,6 +41,7 @@ end dummy_time;
architecture Behavioral of dummy_time is
signal OneSecond: std_logic;
signal init_time: std_logic;
signal tm_cycles_Aux: std_logic_vector(27 downto 0);
signal tm_utc_Aux: std_logic_vector(39 downto 0);
constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
......@@ -58,6 +58,7 @@ begin
if(rst_n = '0') then
tm_cycles_Aux <= (others=>'0');
oneSecond <= '0';
init_time <= '0';
elsif(rising_Edge(Clk_sys)) then
if (Tm_cycles_Aux /= MaxCountcycles2) then
tm_cycles_Aux <= tm_cycles_Aux + 1;
......@@ -70,6 +71,7 @@ begin
else
OneSecond <= '0';
end if;
init_time <= '1';
end if;
end process P_CountTM_cycles;
......@@ -89,8 +91,8 @@ begin
end if;
end process P_CountTM_UTC;
tm_cycles <= tm_cycles_Aux;
tm_utc <= tm_utc_Aux;
tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
end Behavioral;
modules/wrsw_dio/wrsw_dio.vhd
View file @ c2e58275
......@@ -21,7 +21,8 @@
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-03 0.1 R.Rodriguez Created
-- 2012-03-03 0.1 Rafa.r Created
-- 2012-03-08 0.2 Javier.d Added wrsw_dio_wb
-------------------------------------------------------------------------------
......@@ -74,12 +75,11 @@ entity wrsw_dio is
architecture rtl of wrsw_dio is
-- COMPONENT ONLY FOR DEBUGGING
-- Component only for debugging (in order to generate UTC time)
component dummy_time is
port(
clk_sys : in std_logic;
rst_n: in std_logic;
rst_n : in std_logic;
tm_utc : out std_logic_vector(39 downto 0);
tm_cycles : out std_logic_vector(27 downto 0));
end component;
......@@ -310,7 +310,7 @@ end component;
signal dio_tsf_wr_full : std_logic_vector (4 downto 0);
signal dio_tsf_wr_empty : std_logic_vector (4 downto 0);
signal dio_tsf_tag_utc : t_utc_array;
signal dio_tsf_tag_cycles: t_cycles_array;
signal dio_tsf_tag_cycles : t_cycles_array;
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
......@@ -343,8 +343,10 @@ end component;
-- DIO OUT SIGNAL
signal dio_out : std_logic_vector (4 downto 0);
begin -- rtl
-------------------------------------------------------------------------------
-- rtl
-------------------------------------------------------------------------------
begin
-- Dummy counter for simulationg WRPC utc time
U_dummy: dummy_time
......@@ -356,7 +358,9 @@ begin -- rtl
);
------------------------------------------------------------------------------
-- GEN AND STAMPER
------------------------------------------------------------------------------
gen_pulse_modules : for i in 0 to 4 generate
U_pulse_gen : pulse_gen
port map(
......@@ -374,12 +378,10 @@ begin -- rtl
trig_utc_i => trig_utc(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i)
);
trig_valid_p1_i => trig_valid_p1(i));
dio_out_o(i) <= dio_out(i);
U_pulse_stamper : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
......@@ -394,8 +396,8 @@ begin -- rtl
tag_utc_o => tag_utc(i),
tag_cycles_o => tag_cycles(i),
tag_valid_p1_o => tag_valid_p1(i)
);
tag_valid_p1_o => tag_valid_p1(i));
end generate gen_pulse_modules;
......@@ -491,7 +493,7 @@ begin -- rtl
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
-- DEBUG: BE CAREFULL, dio_out disconected from GPIO because it is used in
-- pulse_gen module!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- pulse_gen module!
--dio_out_o(i) <= gpio_out(4*i);
-- END DEBUG
dio_oe_n_o(i) <= gpio_out(4*i+1);
......@@ -505,7 +507,6 @@ begin -- rtl
dio_sdn_ck_n_o <= gpio_out(30);
dio_sdn_n_o <= gpio_out(31);
--??????????????????????????
--gpio_in(30) <= prsnt_m2c_l;
------------------------------------------------------------------------------
-- WB UTC-BASED PULSE GENERATION & INPUT STAMPING
......@@ -513,7 +514,6 @@ begin -- rtl
U_utc_wbslave : wrsw_dio_wb
port map(
rst_n_i => rst_n_i,
-- TAKEN FROM 'wishbone_pkg.vhd'.
wb_clk_i => clk_sys_i,
wb_addr_i => cbar_master_out(3).adr(5 downto 0),
wb_data_i => cbar_master_out(3).dat,
......@@ -541,7 +541,6 @@ begin -- rtl
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
dio_tsf2_wr_full_o => dio_tsf_wr_full(2),
dio_tsf2_wr_empty_o => dio_tsf_wr_empty(2),
......@@ -592,21 +591,21 @@ begin -- rtl
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
TRIG0 <= tag_utc(0)(31 downto 0);
TRIG1(27 downto 0)<= tag_cycles(0)(27 downto 0);
TRIG1(27 downto 0) <= tag_cycles(0)(27 downto 0);
TRIG2 <= tm_utc(31 downto 0);
TRIG3 <= tm_cycles(26 downto 0) & dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
TRIG3 <= tm_cycles(21 downto 0) & dio_tsf_wr_empty(4 downto 0) & dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
--TRIG3(4 downto 0) <= dio_tsf_wr_req(0) & tag_valid_p1(0) & gpio_out(1) & dio_in_i(0) & dio_out(0);
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
-- UTC timestamped FIFO-no-empty interrupts
-- UTC timestamped FIFO-no-empty interrupts
irq_fifos : for i in 0 to 4 generate
irq_nempty(i) <= dio_tsf_wr_empty(i);
irq_nempty(i) <= not dio_tsf_wr_empty(i);
process(clk_sys_i, rst_n_i)
begin
......@@ -626,8 +625,9 @@ begin -- rtl
end if;
end if;
end process;
end generate irq_fifos;
end rtl;
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