Fix indentation.

e58dc553 · Miguel Jimenez Lopez · ea659890 · 4e5e3dfc · e58dc553 · e58dc553
Commit e58dc553 authored Aug 27, 2019 by Miguel Jimenez Lopez
13 changed files
--- a/wr-cores @ 4e5e3dfc
+++ b/wr-cores @ 4e5e3dfc
-Subproject commit f0519a1f5f7f2261b861e6a6d4562e2bec875fb4
+Subproject commit 4e5e3dfc01e395a81d9403bd1e150560972685f7
--- a/hdl/modules/wr_dio/dummy_time.vhd
+++ b/hdl/modules/wr_dio/dummy_time.vhd
@@ -23,7 +23,6 @@
 -- http://www.gnu.org/licenses/lgpl-2.1.html                  
 -------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 --use IEEE.NUMERIC_STD.ALL;
@@ -31,7 +30,7 @@ use ieee.std_logic_unsigned.all;
 entity dummy_time is
  port(clk_sys   : in  std_logic;       -- data output reference clock 125MHz
-	     rst_n: in std_logic; -- system reset
+       rst_n     : in  std_logic;       -- system reset
       -- utc time in seconds     
       tm_utc    : out std_logic_vector(39 downto 0);
       -- number of clk_ref_i cycles
@@ -40,30 +39,30 @@ end dummy_time;
 architecture Behavioral of dummy_time is
-	signal OneSecond: std_logic;
+  signal OneSecond         : std_logic;
-	signal init_time: std_logic;	
+  signal init_time         : std_logic;
-	signal tm_cycles_Aux: std_logic_vector(27 downto 0);
+  signal tm_cycles_Aux     : std_logic_vector(27 downto 0);
-	signal tm_utc_Aux: std_logic_vector(39 downto 0);
+  signal tm_utc_Aux        : std_logic_vector(39 downto 0);
-	constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
+  constant MaxCountcycles1 : std_logic_vector(27 downto 0) := "0111011100110101100100111111";  --125.000.000-1
-	constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
+  constant MaxCountcycles2 : std_logic_vector(27 downto 0) := "0111011100110101100101000000";  --125.000.000
-	constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
+  constant AllOnesUTC      : std_logic_vector(39 downto 0) := (others => '1');
 begin
 ---------------------------------------
 -- Process to count cycles in a second
 ---------------------------------------
-P_CountTM_cycles:
+  P_CountTM_cycles :
-process(rst_n, clk_sys)
+  process(rst_n, clk_sys)
-begin
+  begin
    if(rst_n = '0') then
-		tm_cycles_Aux <= (others=>'0');
+      tm_cycles_Aux <= (others => '0');
      oneSecond     <= '0';
      init_time     <= '0';
    elsif(rising_Edge(Clk_sys)) then
      if (Tm_cycles_Aux /= MaxCountcycles2) then
        tm_cycles_Aux <= tm_cycles_Aux + 1;
      else
-			tm_cycles_Aux <= (others=>'0');
+        tm_cycles_Aux <= (others => '0');
      end if;
      if(Tm_cycles_Aux = MaxCountcycles1) then
@@ -73,26 +72,25 @@ begin
      end if;
      init_time <= '1';
    end if;
-end process P_CountTM_cycles;
+  end process P_CountTM_cycles;
-P_CountTM_UTC:
+  P_CountTM_UTC :
-process(rst_n, clk_sys)
+  process(rst_n, clk_sys)
-begin
+  begin
    if(rst_n = '0') then
-		tm_utc_Aux <= (others=>'0');
+      tm_utc_Aux <= (others => '0');
    elsif(rising_edge(Clk_sys)) then
-		if (OneSecond='1') then
+      if (OneSecond = '1') then
        if (tm_utc_Aux /= AllOnesUTC) then
          tm_utc_Aux <= tm_utc_Aux + 1;
        else
-				tm_utc_Aux <= (others=>'0');
+          tm_utc_Aux <= (others => '0');
        end if;
      end if;
    end if;
-end process P_CountTM_UTC;
+  end process P_CountTM_UTC;
-tm_cycles <= tm_cycles_Aux when init_time = '1' else (others=>'1');
+  tm_cycles <= tm_cycles_Aux when init_time = '1' else (others => '1');
-tm_utc <= tm_utc_Aux when init_time = '1' else (others=>'1');
+  tm_utc    <= tm_utc_Aux    when init_time = '1' else (others => '1');
 end Behavioral;
--- a/hdl/modules/wr_dio/immed_pulse_counter.vhd
+++ b/hdl/modules/wr_dio/immed_pulse_counter.vhd
@@ -27,7 +27,6 @@
 -- http://www.gnu.org/licenses/lgpl-2.1.html                  
 -------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -65,71 +64,68 @@ architecture rtl of immed_pulse_counter is
  signal nozerolength, nozerolength_aux                                 : boolean;
  -- Aux
-  constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others=>'0');  
+  constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others => '0');
 begin  -- architecture rtl
+  synchronization : process(clk_i, rst_n_i)
-  synchronization: process(clk_i, rst_n_i)
  begin
-	 if (rst_n_i='0') then
+    if (rst_n_i = '0') then
-		pulse_start_d0  <='0';
+      pulse_start_d0 <= '0';
-		pulse_start_d1  <='0';
+      pulse_start_d1 <= '0';
-		pulse_start_d2  <='0';		
+      pulse_start_d2 <= '0';
-		pulse_start_d3  <='0';		
+      pulse_start_d3 <= '0';
    elsif rising_edge(clk_i) then
-		pulse_start_d0<=pulse_start_i;
+      pulse_start_d0   <= pulse_start_i;
-		pulse_start_d1<=pulse_start_d0;
+      pulse_start_d1   <= pulse_start_d0;
-		pulse_start_d2<=pulse_start_d1;
+      pulse_start_d2   <= pulse_start_d1;
-	   pulse_start_d3<=pulse_start_d2;
+      pulse_start_d3   <= pulse_start_d2;
-		nozerolength_aux<=pulse_length_i/=zeros;
+      nozerolength_aux <= pulse_length_i /= zeros;
-		if (pulse_start_d2='1' and pulse_start_d1='0') then
+      if (pulse_start_d2 = '1' and pulse_start_d1 = '0') then
-			nozerolength<=nozerolength_aux;
+        nozerolength <= nozerolength_aux;
      end if;
    end if;
  end process;
  state_process : process(clk_i, rst_n_i)
  begin
-	 if (rst_n_i='0') then
+    if (rst_n_i = '0') then
-      counter      <=(others=>'0');
+      counter <= (others => '0');
-      state        <=WAIT_ST;
+      state   <= WAIT_ST;
    elsif rising_edge(clk_i) then
      case state is
        when WAIT_ST =>
-		    if pulse_start_d3='1' and nozerolength then
+          if pulse_start_d3 = '1' and nozerolength then
-			   state   <=COUNTING;
+            state   <= COUNTING;
-				counter <=unsigned(pulse_length_i)-1;
+            counter <= unsigned(pulse_length_i)-1;
          else
-			    state<=WAIT_ST;
+            state <= WAIT_ST;
          end if;
        when COUNTING =>
-		    if (counter=0) then
+          if (counter = 0) then
            state <= WAIT_ST;
          else
            state   <= COUNTING;
-				counter<=counter-1;
+            counter <= counter-1;
          end if;
        when others =>
-		    state<=WAIT_ST;
+          state <= WAIT_ST;
      end case;
    end if;
  end process;
+  output_process : process(counter, state)
-  output_process:process(counter, state)
  begin
-    if (rst_n_i='0') then
+    if (rst_n_i = '0') then
-      pulse_output_o <='0';
+      pulse_output_o <= '0';
    else
      case state is
        when WAIT_ST =>
-          pulse_output_o <='0';
+          pulse_output_o <= '0';
        when COUNTING =>
-			   pulse_output_o <='1';
+          pulse_output_o <= '1';
        when others =>
-          pulse_output_o <='0';
+          pulse_output_o <= '0';
      end case;
    end if;
  end process;

--- a/hdl/modules/wr_dio/pulse_gen_pl.vhd
+++ b/hdl/modules/wr_dio/pulse_gen_pl.vhd
--- a/hdl/modules/wr_dio/wr_dio.vhd
+++ b/hdl/modules/wr_dio/wr_dio.vhd
@@ -6,7 +6,7 @@
 -- Author     : Javier Díaz
 -- Company    : Seven Solutions
 -- Created    : 2012-07-25
-- Last update: 2012-07-25
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -81,7 +81,7 @@ entity wr_dio is
    TRIG3 : out std_logic_vector(31 downto 0)
    );
-  end wr_dio;
+end wr_dio;
 architecture rtl of wr_dio is
@@ -130,10 +130,10 @@ architecture rtl of wr_dio is
  signal wb_out : t_wishbone_slave_out;
  signal wb_in  : t_wishbone_slave_in;
-------------------------------------------------------------------------------
 begin
-U_WRAPPER_DIO : xwr_dio
+  U_WRAPPER_DIO : xwr_dio
    generic map (
      g_interface_mode      => g_interface_mode,
      g_address_granularity => g_address_granularity)
@@ -185,7 +185,7 @@ U_WRAPPER_DIO : xwr_dio
  wb_dat_o   <= wb_out.dat;
  wb_ack_o   <= wb_out.ack;
  wb_stall_o <= wb_out.stall;
-----------------------------------------------------------------------------------	
 end rtl;

--- a/hdl/modules/wr_dio/wr_dio_pkg.vhd
+++ b/hdl/modules/wr_dio/wr_dio_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Javier Díaz
 -- Company    : Seven Solutions, UGR
 -- Created    : 2012-07-18
-- Last update: 2012-06-19
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -85,7 +85,7 @@ package body wr_dio_pkg is
  function f_xwb_bridge_product_manual_sdb(
    g_size        : t_wishbone_address;
    g_sdb_addr    : t_wishbone_address;
-	 g_sdb_product: t_sdb_product) return t_sdb_bridge	 
+    g_sdb_product : t_sdb_product) return t_sdb_bridge
  is
    variable result : t_sdb_bridge;
  begin
@@ -109,7 +109,7 @@ package body wr_dio_pkg is
    g_wraparound  : boolean := true;
    g_layout      : t_sdb_record_array;
    g_sdb_addr    : t_wishbone_address;
-	 g_sdb_product: t_sdb_product) return t_sdb_bridge	
+    g_sdb_product : t_sdb_product) return t_sdb_bridge
  is
    alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;

--- a/hdl/modules/wr_dio/wr_dio_wb.vhd
+++ b/hdl/modules/wr_dio/wr_dio_wb.vhd
--- a/hdl/modules/wr_dio/xwr_dio.vhd
+++ b/hdl/modules/wr_dio/xwr_dio.vhd
@@ -6,7 +6,7 @@
 -- Author     : Rafael Rodriguez, Javier Daz
 -- Company    : Seven Solutions
 -- Created    : 2012-03-03
-- Last update: 2013-08-07
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -82,7 +82,7 @@ entity xwr_dio is
    TRIG2 : out std_logic_vector(31 downto 0);
    TRIG3 : out std_logic_vector(31 downto 0)
    );
-  end xwr_dio; 
+end xwr_dio;
 architecture rtl of xwr_dio is
@@ -398,10 +398,10 @@ architecture rtl of xwr_dio is
  -- WB SDB Crossbar
  constant c_diobar_layout : t_sdb_record_array(3 downto 0) :=
-    (0 => f_sdb_embed_device(c_xwb_onewire_master_sdb ,   x"00000000"), -- ONEWIRE
+    (0 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00000000"),  -- ONEWIRE
-     1 => f_sdb_embed_device(c_xwb_i2c_master_sdb     ,   x"00000100"), -- I2C
+     1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000100"),      -- I2C
-     2 => f_sdb_embed_device(c_xwb_gpio_port_sdb      ,   x"00000200"), -- GPIO
+     2 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00000200"),       -- GPIO
-     3 => f_sdb_embed_device(c_xwr_dio_wb_sdb       ,   x"00000300")  -- DIO REGISTERS
+     3 => f_sdb_embed_device(c_xwr_dio_wb_sdb, x"00000300")  -- DIO REGISTERS
     );
  constant c_diobar_sdb_address : t_wishbone_address := x"00000400";
@@ -544,7 +544,7 @@ begin
  scl_pad_in <= dio_scl_b;
  sda_pad_in <= dio_sda_b;
-  dio_ga_o<="00"; -- Innused because SPEC boards have these fmc signals to ground
+  dio_ga_o   <= "00";  -- Innused because SPEC boards have these fmc signals to ground
  ------------------------------------------------------------------------------
  -- WB GPIO PORT
@@ -605,8 +605,8 @@ begin
  slave_o.err   <= slave_bypass_o.err;
  slave_o.rty   <= slave_bypass_o.rty;
-  immediate_output_with_pulse_length: for i in 0 to 4 generate
+  immediate_output_with_pulse_length : for i in 0 to 4 generate
-    immediate_output_component: immed_pulse_counter
+    immediate_output_component : immed_pulse_counter
      generic map (
        pulse_length_width => 28
        )
@@ -619,12 +619,12 @@ begin
        );
  end generate immediate_output_with_pulse_length;
-  gen_pio_assignment: for i in 0 to 4 generate
+  gen_pio_assignment : for i in 0 to 4 generate
    gpio_in(c_IOMODE_NB*i) <= dio_in_i(i);
    dio_pulse(i)           <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
    dio_oe_n_o(i)          <= dio_iomode_reg(c_IOMODE_NB*i+2);
    dio_term_en_o(i)       <= dio_iomode_reg(c_IOMODE_NB*i+3);
-    dio_out_o(i) <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i)="00" else dio_pulse(i);
+    dio_out_o(i)           <= gpio_out(c_IOMODE_NB*i) when dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "00" else dio_pulse(i);
    --with dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i)
    --select dio_out_o(i) <=
@@ -635,10 +635,10 @@ begin
  end generate gen_pio_assignment;
-  dio_led_top_o  <=  dio_iomode_reg(c_IOMODE_NB*0+3) OR 
+  dio_led_top_o <= dio_iomode_reg(c_IOMODE_NB*0+3) or
-							dio_iomode_reg(c_IOMODE_NB*1+3) OR
+                   dio_iomode_reg(c_IOMODE_NB*1+3) or
-							dio_iomode_reg(c_IOMODE_NB*2+3) OR
+                   dio_iomode_reg(c_IOMODE_NB*2+3) or
-							dio_iomode_reg(c_IOMODE_NB*3+3) OR
+                   dio_iomode_reg(c_IOMODE_NB*3+3) or
                   dio_iomode_reg(c_IOMODE_NB*4+3);
  --dio_led_top_o  <= gpio_out(27); --only to test!
@@ -647,7 +647,7 @@ begin
  dio_led_bot_o_ch(0) <= (not dio_iomode_reg(c_IOMODE_NB*0+2) and dio_pps_i);
-  dio_led_bot_asig: for i in 1 to 4 generate
+  dio_led_bot_asig : for i in 1 to 4 generate
    dio_led_bot_o_ch(i) <= (not dio_iomode_reg(c_IOMODE_NB*i+2) and dio_pulse(i));
  end generate dio_led_bot_asig;
@@ -681,8 +681,8 @@ begin
  ------------------------------------------------------------------------------
  -- WB DIO control registers
  ------------------------------------------------------------------------------  
-  wb_dio_slave_out.err<='0';
+  wb_dio_slave_out.err <= '0';
-  wb_dio_slave_out.rty<='0';
+  wb_dio_slave_out.rty <= '0';
  -- SUPPORTING PIPELINE WBGEN2 SLAVES
  U_DIO_REGISTERS : wr_dio_wb
@@ -794,11 +794,11 @@ begin
      irq_trigger_ready_3_i => trig_ready(3),
      irq_trigger_ready_4_i => trig_ready(4),
-      dio_prog0_pulse_length_o=> pulse_length(0),
+      dio_prog0_pulse_length_o => pulse_length(0),
-      dio_prog1_pulse_length_o=> pulse_length(1),
+      dio_prog1_pulse_length_o => pulse_length(1),
-      dio_prog2_pulse_length_o=> pulse_length(2),
+      dio_prog2_pulse_length_o => pulse_length(2),
-      dio_prog3_pulse_length_o=> pulse_length(3),
+      dio_prog3_pulse_length_o => pulse_length(3),
-      dio_prog4_pulse_length_o=> pulse_length(4),
+      dio_prog4_pulse_length_o => pulse_length(4),
      dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
      dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
@@ -825,12 +825,12 @@ begin
          dio_tsf_tag_seconds(i) <= (others => '0');
          dio_tsf_tag_cycles(i)  <= (others => '0');
        else
-            if ((tag_valid_p1(i) = '1') AND (dio_tsf_wr_full(i)='0')) then
+          if ((tag_valid_p1(i) = '1') and (dio_tsf_wr_full(i) = '0')) then
-              dio_tsf_wr_req(i)      <='1';
+            dio_tsf_wr_req(i)      <= '1';
-              dio_tsf_tag_seconds(i) <=tag_seconds(i);
+            dio_tsf_tag_seconds(i) <= tag_seconds(i);
-              dio_tsf_tag_cycles(i)  <=tag_cycles(i);
+            dio_tsf_tag_cycles(i)  <= tag_cycles(i);
          else
-              dio_tsf_wr_req(i)      <='0';
+            dio_tsf_wr_req(i) <= '0';
          end if;
        end if;
      end if;
@@ -859,7 +859,7 @@ begin
 -----------------------------------------------------------------------------------
 ------ signals for debugging
 -----------------------------------------------------------------------------------
-     TRIG0(21 downto 0 ) <= tag_seconds(0)(21 downto 0);
+  TRIG0(21 downto 0)  <= tag_seconds(0)(21 downto 0);
  TRIG0(22)           <= irq_nempty(0);
  TRIG0(23)           <= tm_time_valid_i;
  TRIG0(31 downto 24) <= pulse_length(0)(7 downto 0);
@@ -867,8 +867,8 @@ begin
  TRIG1(29)           <= slave_bypass_o.ack;
  TRIG1(30)           <= dio_pulse(0);
  TRIG1(31)           <= gpio_out(0);
-     --TRIG3(2 downto 0)   <= 
+--TRIG3(2 downto 0)   <= 
-     --TRIG3(4 downto 0)  <= 
+--TRIG3(4 downto 0)  <= 
 -----------------------------------------------------------------------------------
 -----------------------------------------------------------------------------------
 -----------------------------------------------------------------------------------     

--- a/hdl/top/dio-common/dio_common_top.vhd
+++ b/hdl/top/dio-common/dio_common_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Miguel Jimenez-Lopez
 -- Company    : Seven Solutions
 -- Created    : 2019-03-27
-- Last update: 2019-03-27
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -295,8 +295,8 @@ architecture top of dio_common_top is
  signal wrc_abscal_txts_out       : std_logic;
  signal wrc_abscal_rxts_out       : std_logic;
  signal wrc_pps_out               : std_logic;
-  attribute IOB: string;
+  attribute IOB                    : string;
-  attribute IOB of wrc_pps_out: signal is "TRUE";
+  attribute IOB of wrc_pps_out     : signal is "TRUE";
  signal wrc_pps_csync_out         : std_logic;
  signal wrc_pps_csync_out_ext     : std_logic;
  signal wrc_pps_csync_out_ext_int : std_logic;
@@ -342,8 +342,8 @@ begin  -- architecture top
    generic map (
      g_num_masters => c_NUM_WB_MASTERS,
      g_num_slaves  => c_NUM_WB_SLAVES,
-      g_registered  => TRUE,
+      g_registered  => true,
-      g_wraparound  => TRUE,
+      g_wraparound  => true,
      g_layout      => f_pick_sdb_layout_for_dio(g_dio_mode),
      g_sdb_addr    => c_SDB_ADDRESS)
    port map (
@@ -405,9 +405,9 @@ begin  -- architecture top
      ---------------------------------------------------------
      -- DMA registers wishbone interface (slave classic)
      dma_reg_clk_i => clk_sys_62m5,
-      dma_reg_adr_i => (others=>'0'),
+      dma_reg_adr_i => (others => '0'),
-      dma_reg_dat_i => (others=>'0'),
+      dma_reg_dat_i => (others => '0'),
-      dma_reg_sel_i => (others=>'0'),
+      dma_reg_sel_i => (others => '0'),
      dma_reg_stb_i => '0',
      dma_reg_we_i  => '0',
      dma_reg_cyc_i => '0',
@@ -430,7 +430,7 @@ begin  -- architecture top
      ---------------------------------------------------------
      -- L2P DMA Interface (Pipelined Wishbone master)
      dma_clk_i   => clk_sys_62m5,
-      dma_dat_i   => (others=>'0'),
+      dma_dat_i   => (others => '0'),
      dma_ack_i   => '1',
      dma_stall_i => '0',
      dma_err_i   => '0',
@@ -447,7 +447,7 @@ begin  -- architecture top
  cmp_xwrc_board_spec : xwrc_board_spec
    generic map (
      g_simulation                => g_simulation,
-      g_with_external_clock_input => TRUE,
+      g_with_external_clock_input => true,
      g_dpram_initf               => g_dpram_initf,
      g_fabric_iface              => f_pick_fabric_iface_for_dio(g_dio_mode))
    port map (
@@ -582,8 +582,8 @@ begin  -- architecture top
  ------------------------------------------------------------------------------
  -- Digital I/O FMC Mezzanine connections
  ------------------------------------------------------------------------------
-  gen_dio_ibufs: for I in 0 to 4 generate
+  gen_dio_ibufs : for I in 0 to 4 generate
-    U_ibuf: IBUFDS
+    U_ibuf : IBUFDS
      generic map (
        DIFF_TERM => true)
      port map (
@@ -620,7 +620,7 @@ begin  -- architecture top
    end if;
  end process;
-  cmp_ibugds_extref: IBUFGDS
+  cmp_ibugds_extref : IBUFGDS
    generic map (
      DIFF_TERM => true)
    port map (

--- a/hdl/top/dio-common/dio_common_top_pkg.vhd
+++ b/hdl/top/dio-common/dio_common_top_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Miguel Jimenez-Lopez
 -- Company    : Seven Solutions
 -- Created    : 2019-03-27
-- Last update: 2019-03-27
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -216,24 +216,24 @@ package dio_common_top_pkg is
 -- f_xwb_bridge_manual_sdb(size, sdb_addr)
 -- Note: sdb_addr is the sdb records address relative to the bridge base address
-constant c_wrc_bridge_sdb : t_sdb_bridge :=
+  constant c_wrc_bridge_sdb : t_sdb_bridge :=
    f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-constant c_nic_bridge_sdb : t_sdb_bridge :=
+  constant c_nic_bridge_sdb : t_sdb_bridge :=
    f_xwb_bridge_manual_sdb(x"0001ffff", x"00011000");
-constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
+  constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
    f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000400", c_xwr_dio_sdb);
 -- Primary wishbone crossbar layout (NIC)
-constant c_NIC_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+  constant c_NIC_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
    c_WB_SLAVE_WRC     => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
    c_WB_SLAVE_NIC_VIC => f_sdb_embed_bridge(c_nic_bridge_sdb, x"00040000"),  -- NIC
    c_WB_SLAVE_DIO     => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00060000")  -- DIO
    );
 -- Primary wishbone crossbar layout (NIC)
-constant c_VIC_ONLY_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+  constant c_VIC_ONLY_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
    c_WB_SLAVE_WRC     => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
-  c_WB_SLAVE_NIC_VIC => f_sdb_embed_device(c_xwb_vic_sdb , x"00040000"), -- VIC
+    c_WB_SLAVE_NIC_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00040000"),  -- VIC
    c_WB_SLAVE_DIO     => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00060000")  -- DIO
    );

--- a/hdl/top/dio-etherbone/dio_etherbone_top.vhd
+++ b/hdl/top/dio-etherbone/dio_etherbone_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Miguel Jimenez-Lopez
 -- Company    : Seven Solutions
 -- Created    : 2019-03-27
-- Last update: 2019-03-27
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------

--- a/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
+++ b/hdl/top/dio-ext-nic-etherbone/dio_ext_nic_etherbone_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk, Rafael Rodriguez, Javier Daz, Miguel Jimenez
 -- Company    : Elproma, Seven Solutions, UGR
 -- Created    : 2012-02-08
-- Last update: 2019-03-27
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -321,9 +321,9 @@ architecture top of dio_ext_nic_etherbone_top is
  -- Primary wishbone crossbar layout
  constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
    c_WB_SLAVE_WRC   => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"),  -- WRPC
-    c_WB_SLAVE_NIC => f_sdb_embed_device(c_xwr_nic_sdb , x"00040000"),     -- NIC
+    c_WB_SLAVE_NIC   => f_sdb_embed_device(c_xwr_nic_sdb, x"00040000"),  -- NIC
-    c_WB_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb , x"00060000"),  -- VIC (IRQ gen)
+    c_WB_SLAVE_VIC   => f_sdb_embed_device(c_xwb_vic_sdb, x"00060000"),  -- VIC (IRQ gen)
-    c_WB_SLAVE_TXTSU => f_sdb_embed_device(c_xwr_txtsu_sdb , x"00061000"),   -- TxTSU
+    c_WB_SLAVE_TXTSU => f_sdb_embed_device(c_xwr_txtsu_sdb, x"00061000"),  -- TxTSU
    c_WB_SLAVE_DIO   => f_sdb_embed_bridge(c_wr_dio_bridge_sdb, x"00062000")  -- DIO
    );
@@ -384,8 +384,8 @@ architecture top of dio_ext_nic_etherbone_top is
  signal wrc_pps_out               : std_logic;
  signal wrc_pps_csync_out_ext_int : std_logic;
  signal wrc_pps_csync_out_ext     : std_logic;
-  attribute IOB: string;
+  attribute IOB                    : string;
-  attribute IOB of wrc_pps_out: signal is "TRUE";
+  attribute IOB of wrc_pps_out     : signal is "TRUE";
  signal wrc_pps_csync             : std_logic;
  signal wrc_pps_valid             : std_logic;
  signal wrc_pps_valid_out_ext_int : std_logic;
@@ -442,8 +442,8 @@ begin  -- architecture top
      generic map (
        g_num_masters => c_NUM_WB_MASTERS,
        g_num_slaves  => c_NUM_WB_SLAVES,
-        g_registered  => TRUE,
+        g_registered  => true,
-        g_wraparound  => TRUE,
+        g_wraparound  => true,
        g_layout      => c_WB_LAYOUT,
        g_sdb_addr    => c_SDB_ADDRESS)
      port map (
@@ -463,8 +463,8 @@ begin  -- architecture top
      generic map (
        g_num_masters => c_NUM_WB_MASTERS-1,
        g_num_slaves  => c_NUM_WB_SLAVES,
-        g_registered  => TRUE,
+        g_registered  => true,
-        g_wraparound  => TRUE,
+        g_wraparound  => true,
        g_layout      => c_WB_LAYOUT,
        g_sdb_addr    => c_SDB_ADDRESS)
      port map (
@@ -527,9 +527,9 @@ begin  -- architecture top
      ---------------------------------------------------------
      -- DMA registers wishbone interface (slave classic)
      dma_reg_clk_i => clk_sys_62m5,
-      dma_reg_adr_i => (others=>'0'),
+      dma_reg_adr_i => (others => '0'),
-      dma_reg_dat_i => (others=>'0'),
+      dma_reg_dat_i => (others => '0'),
-      dma_reg_sel_i => (others=>'0'),
+      dma_reg_sel_i => (others => '0'),
      dma_reg_stb_i => '0',
      dma_reg_we_i  => '0',
      dma_reg_cyc_i => '0',
@@ -552,7 +552,7 @@ begin  -- architecture top
      ---------------------------------------------------------
      -- L2P DMA Interface (Pipelined Wishbone master)
      dma_clk_i   => clk_sys_62m5,
-      dma_dat_i   => (others=>'0'),
+      dma_dat_i   => (others => '0'),
      dma_ack_i   => '1',
      dma_stall_i => '0',
      dma_err_i   => '0',
@@ -569,7 +569,7 @@ begin  -- architecture top
  cmp_xwrc_board_spec : xwrc_board_spec
    generic map (
      g_simulation                => g_simulation,
-      g_with_external_clock_input => TRUE,
+      g_with_external_clock_input => true,
      g_dpram_initf               => g_dpram_initf,
      g_fabric_iface              => PLAIN,
      g_aux_sdb                   => c_etherbone_sdb)
@@ -708,8 +708,8 @@ begin  -- architecture top
  ------------------------------------------------------------------------------
  -- Digital I/O FMC Mezzanine connections
  ------------------------------------------------------------------------------
-  gen_dio_ibufs: for I in 0 to 4 generate
+  gen_dio_ibufs : for I in 0 to 4 generate
-    U_ibuf: IBUFDS
+    U_ibuf : IBUFDS
      generic map (
        DIFF_TERM => true)
      port map (
@@ -746,7 +746,7 @@ begin  -- architecture top
    end if;
  end process;
-  cmp_ibugds_extref: IBUFGDS
+  cmp_ibugds_extref : IBUFGDS
    generic map (
      DIFF_TERM => true)
    port map (

--- a/hdl/top/dio-nic/dio_nic_top.vhd
+++ b/hdl/top/dio-nic/dio_nic_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Miguel Jimenez-Lopez
 -- Company    : Seven Solutions
 -- Created    : 2019-03-27
-- Last update: 2019-03-27
+-- Last update: 2019-08-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------