FMC 5-channel Digital I/O module
Functional specifications
- 5 input/output ports (Lemo 00 connectors)
- Output levels: LVTTL, capable of driving +3.3 V over a 50-Ohm load. At power-up the outputs should be in Hi-Z state.
- Input levels: any logic standard from Vih = 1 V to Vih = 5 V (programmable threshold).
- Output Rise/fall times: max. 2 ns
- Input bandwidth: min. 200 MHz
- Programmable 50-Ohm input termination in each channel.
- LVDS I/O on the carrier side.
- One of the inputs shall be capable of driving a global clock net in the carrier's FPGA.
- Inputs need to be protected against +15V pulses with a pulse width of at least 10us @ 50Hz (with protection diodes if possible).
- Need to withstand a continuous short-circuit on all the outputs at the same time.
Project Status
Date | Event |
27-05-2011 | Start of brainstorming. |
19-07-2011 | Five cards built. Contains bugs. |
12-08-2011 | Schematics should be updated before passing through CERN's design office. |
Tom Wlostowski, Erik van der Bij - 12 August 2011