FMC masterFIP
FMC-masterFIP is an interface card for the
WorldFIP network
in an LPC FMC form-factor.
It is used as the physical layer interface of the
masterFIP
project.
Top view of the masterFIP board*
Bottom view of the masterFIP
board
The main components of the FMC-masterFIP board are:
- The FielDrive bus driver and FieldTR insulating transformer, both developed and sold by the company Alstom.
- A Lemo-0 connector, optionally used for the reception of an input synchronization trigger pulse, usually from CERN's timing board CTRI.
- An EEPROM chip, loaded with IPMI FRU information, and a 1-wire thermometer-unique-id-chip, so as to comply with the FMC standard.
The schematics of the board, drawn in Altium, are available at CERN's
EDMS. As the following table
shows, three versions of the board have been designed.
A list of issues that were being identified and led to the development
of a new version is available in the issues
tab of this
project.
Different board executions exist depending on the WorldFIP communication
speed: 31.25kbps, 1Mbps, 2.5Mbps, and 5Mbps; a set of ten components
differentiates the board executions.
Specifications
Parameter | Value |
Form-factor | FMC, LPC connector |
WorldFIP connector | Micro Sub-D 9 pins |
WorldFIP interface | FielDrive + FieldTR (Alstom) |
Bus speed | 31.25k, 1M, 2.5M, 5M (different executions of hardware) |
External sync. input | Optional sync of the WorldFIP start of macrocycle; LEMO 0 connector; TTL; Software selectable 50 Ohms termination |
Project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03098
- Currently supported versions:
- FmcWorldFIP V3 - Bus speed 31.25k - EDA-03098-V3-0
- FmcWorldFIP V3 - Bus speed 1M - EDA-03098-V3-1
- FmcWorldFIP V3 - Bus speed 2.5M - EDA-03098-V3-2
- FmcWorldFIP V3 - Bus speed 5M - EDA-03098-V3-3
Version | Schematics | Comments |
V1 | EDA-03098-V1-0, EDA-03098-V1-1, EDA-03098-V1-2, EDA-03098-V1-3 | First version |
V2 | EDA-03098-V2-0, EDA-03098-V2-1, EDA-03098-V2-2, EDA-03098-V2-3 | Corrections on V1 |
V3 | EDA-03098-V3-0, EDA-03098-V3-1, EDA-03098-V3-2, EDA-03098-V3-3 | V2 simplified, without ADC |
Support
Contacts
Eva Gousiou - CERN | Erik van der Bij - CERN | Matthieu Cattin †, designer - CERN
Project Status
Date | Event |
10-2014 | Schematics work started |
12-2014 | Schematics ready for layout |
01-2015 | Board layout done at CERN by DEM |
01-2015 | Layout review |
02-2015 | Layout modification ready |
02-2015 | First brainstorm about gateware and firmware |
03-2015 | Production files finalised, 3 prototypes ordered |
04-2015 | Designer Matthieu Cattin † |
04-2015 | 3 assembled prototypes received, 5 empty PCBs available |
07-2015 | One board tested that sent and received WorldFIP data. ADC not tested. |
02-2016 | Production Test program being written by a company. ADC testing is part of it. |
10-2016 | Schematics review for V2 |
12-2016 | Layout review for V2 |
01-2017 | Hardware V3 ready for production; ADC diagnostics removed based on high production and maintenance costs. |
20-01-2017 | Ordered 15 V3 prototype cards. |
28-03-2017 | 15 V3 prototype cards received, ready for testing. |
Matthieu Cattin, Eva Gousiou, Erik van der Bij, 28 March 2017