1) Remove RL2
Probing on the bus side of the transformer could potentially damage the
Removing RL2 will remove the possibility of diagnosing errors on the
transformer, but those are not frequent (no transformer error in 10
years and hundreds of nodes has been reported; check
the list of all WorldFIP related errors; a FielDrive has been found
faulty twice, but there is no FieldTR error reported).
The removal could also ease the rerouting described in point 2 below.
(*) A general rule of thumb is to not worry about transmission line
effects until the transmission line reaches λ/10.
In our case, the 10ns max rise/fall time of the WorldFIP signal (see
page 25 of FielDrive
translates to f=35MHz (BW=0.35/Tr) and λ=5m (λ = c/f and speed of EM
waves in copper is about 2/3 c).
Therefore as soon as our track lengths are < 50cm we should not worry
about transmission line effects.
In the V2 version the track lengths from the front connector to the
FieldTR are 10mm long and from the FieldTR to the FielDrive 50mm, which
is an order of magnitude less than the 50cm threshold.
3) Change the behavior of the RL1 relay control so that 'highZ' and
'0' keep the relay OFF
|Version|Transistor Gate voltage and Relay behavior| Notes|
|v1|highZ: relay OFF; 0: relay ON; 1: relay in unidentified state| Gate
voltage is directly the output of the FPGA (2.5V)|
|v2 proposal|highZ: relay OFF; 0: relay ON; 1: relay OFF| Gate voltage
is the output of the voltage translator (5V)|
|v2 final| highZ: relay OFF; 0: relay OFF; 1: relay ON| Gate voltage is
the output of the voltage translator (5V) and PMOS changes to NMOS|