# FIRMWARE REPOSITORY FOR THE AIDA2020 TRIGGER LOGIC UNIT

Firmware for the AIDA TLU Hardware
This repository contains the VHL used to generate the firmware for the AIDA TLU, both versions V1C (T-shaped pcb) and V1E (rectangular PCB; the one most likely to be used outside the UoB lab).

Very limited documentation about the unit is stored here.
For a more exhaustive documentation please refer to the [main repository: https://ohwr.org/project/fmc-mtlu](https://ohwr.org/project/fmc-mtlu).


## SCRIPTS
The repository also contains Python scripts used to test the hardware. These scripts rely on a few libraries not linked here, so they are unlikely to work "out of the box".

## EUDAQ2
The best way to operate on the TLU is by using the EUDAQ2 tools (provide link!).

### Building Firmware

The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware.

Set up the environment for Xilinx Vivado, then:

```
# Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3"
TLU_BRANCH=""

mkdir work
cd work

IPBB_VERSION="0.3.13"
curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
# ( or git clone git@github.com:ipbus/ipbb.git )
source ipbb-${IPBB_VERSION}/env.sh

ipbb init build

cd build
ipbb add git https://github.com/ipbus/ipbus-firmware.git ${IPBUS_BRANCH}
ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git ${TLU_BRANCH}
# For read/write load a valid ssh key and use the repo below ....
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git 


# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file"
pushd src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/addr_table
pwd
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/
mv ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
popd

echo "BUILD: patching enclustra_ax3_pm3_infra.vhd"
pushd src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl
dos2unix enclustra_ax3_pm3_infra.vhd
patch  <  ../../../../../../../fmc-mtlu-gw/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.patch
popd

# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
#echo "BUILD: patching enclustra_ax3_pm3.tcl"
#pushd src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf
#patch  <  ../../../../../../../fmc-mtlu-gw/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
#popd

echo "BUILD: ipbb proj create"
ipbb proj create vivado TLU_1e fmc-mtlu-gw:AIDA_tlu/projects/TLU_v1e -t top_tlu_1e_a35.dep
cd proj/TLU_1e

ipbb vivado project

# Set correct file as design "top"
#echo "BUILD: Setting the correct design as top"
#vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr

# Set TLU timing contraints *.xdc file to have "late" processing order
vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl top/top.xpr

echo "BUILD: ipbb impl"
ipbb vivado impl
echo "BUILD: ipbb bitfile"
ipbb vivado bitfile
echo "BUILD: ipbb package"
ipbb vivado package
deactivate
```