# FIRMWARE REPOSITORY FOR THE AIDA2020 TRIGGER LOGIC UNIT

Firmware for the AIDA TLU Hardware
This repository contains the VHL used to generate the firmware for the AIDA TLU, both versions V1C (T-shaped pcb) and V1E (rectangular PCB; the one most likely to be used outside the UoB lab).

Very limited documentation about the unit is stored here.
For a more exhaustive documentation please refer to the [main repository: https://ohwr.org/project/fmc-mtlu](https://ohwr.org/project/fmc-mtlu).


## SCRIPTS
The repository also contains Python scripts used to test the hardware. These scripts rely on a few libraries not linked here, so they are unlikely to work "out of the box".

## EUDAQ2
The best way to operate on the TLU is by using the EUDAQ2 tools (provide link!).

### Obtaining Latest Firmware

The latest version of the firmware should always be available as a zipped archive in the [wiki section](https://ohwr.org/project/fmc-mtlu-gw/wikis/home#firmware-releases).
The zip will contain a *.bit file, *.mcs file and an address map XML file.
The *.bit file is used to program the FPGA one-off, i.e. the image of the firmware will be deleted once the unit is power cycled.
The *.mcs file is used to flash the EEPROM of the FPGA with a permament version of the firmware. This allows the TLU to automatically load this image at start-up.
The XML file is needed to correctly map the FPGA internal registers to the corresponding functions in the software. This file only changes when major modifications are included in the firmware.

The procedure to program the FPGA and the EEPROM are described in the [TLU manual](https://www.ohwr.org/project/fmc-mtlu/blob/master/Documentation/Main_TLU.pdf).

It is always possible to compile the firmware to obtain the *.bit and *.mcs files. This is explained in the next section.

### Building Firmware

The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware together with the Xilinx Vivado software. 

There is a script availble which execute the commands necessary to produce an FPGA configuration file (*.bit file). Instructions are available at https://ohwr.org/project/fmc-mtlu-gw/wikis/Building-AIDA-2020-TLU-firmware

