set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]


proc false_path {patt clk} {
    set p [get_ports -quiet $patt -filter {direction != out}]
    if {[llength $p] != 0} {
        set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
        set_false_path -from [get_ports $patt -filter {direction != out}]
    }
    set p [get_ports -quiet $patt -filter {direction != in}]
    if {[llength $p] != 0} {
       	set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
	    set_false_path -to [get_ports $patt -filter {direction != in}]
	}
}

# System oscillator clock
create_clock -period 10.000 -name osc_clk_100MHz [get_ports osc_clk_100MHz]

set_property IOSTANDARD LVCMOS33 [get_ports osc_clk_100MHz]
set_property PACKAGE_PIN R4 [get_ports osc_clk_100MHz]


#voltage adjust pins
set_property IOSTANDARD LVCMOS25 [get_ports {vadj[*]}]
set_property PACKAGE_PIN AB17 [get_ports {vadj[1]}]
set_property PACKAGE_PIN AA13 [get_ports {vadj[0]}]


set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN T14 [get_ports {leds[0]}]
set_property PACKAGE_PIN T15 [get_ports {leds[1]}]
set_property PACKAGE_PIN T16 [get_ports {leds[2]}]
set_property PACKAGE_PIN U16 [get_ports {leds[3]}]
set_property PACKAGE_PIN V15 [get_ports {leds[4]}]
set_property PACKAGE_PIN W16 [get_ports {leds[5]}]
set_property PACKAGE_PIN W15 [get_ports {leds[6]}]
set_property PACKAGE_PIN Y13 [get_ports {leds[7]}]

set_property IOSTANDARD LVCMOS25 [get_ports rgmii_*]
set_property PACKAGE_PIN Y12 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN W12 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN W11 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN Y11 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN V10 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN AA14 [get_ports rgmii_txc]
set_property PACKAGE_PIN AB16 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN AA15 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN AB15 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN AB11 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN W10 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN V13 [get_ports rgmii_rxc]

set_property IOSTANDARD LVCMOS33 [get_ports phy_rstn]
set_property PACKAGE_PIN U7 [get_ports phy_rstn]

false_path {phy_rstn} osc_clk_100MHz


# UART pins (not always used).
# AA19 bank 0 (config). V18 bank 14, 3v3
set_property IOSTANDARD LVCMOS33 [get_ports {FTDI_*}]
set_property PACKAGE_PIN AA19 [get_ports {FTDI_RXD}]
set_property PACKAGE_PIN V18 [get_ports {FTDI_TXD}]

## Configuration options.
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]


# Configuration pins on bank 16, Vadj.
if { [llength [get_ports {cfg[*]}]] > 0} {
  set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
  set_property PACKAGE_PIN E22 [get_ports {cfg[0]}]
  set_property PACKAGE_PIN F21 [get_ports {cfg[1]}]
  set_property PACKAGE_PIN G21 [get_ports {cfg[2]}]
  set_property PACKAGE_PIN G22 [get_ports {cfg[3]}]
}


# Clock constraints
set_false_path -through [get_pins infra/clocks/rst_reg/Q]
set_false_path -through [get_nets infra/clocks/nuke_i]

# IPbus clock
create_generated_clock -name ipbus_clk -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT3]

# Ethernet clock
create_generated_clock -name clk_125 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT1]
create_generated_clock -name clk_125_90 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT2]

# 200 Mhz derived clock
create_generated_clock -name clk_200 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT4]

# 40 Mhz derived clock
create_generated_clock -name clk_aux -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT5]

# Asynchronous clock groupings
set_clock_groups -asynchronous -group [get_clocks ipbus_clk] -group [get_clocks -include_generated_clocks [get_clocks clk_aux]]
