set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

## Trigger inputs

#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]

set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
set_property PACKAGE_PIN A15 [get_ports {threshold_discr_p_i[0]}]
set_property PACKAGE_PIN A16 [get_ports {threshold_discr_n_i[0]}]
set_property PACKAGE_PIN F13 [get_ports {threshold_discr_p_i[1]}]
set_property PACKAGE_PIN F14 [get_ports {threshold_discr_n_i[1]}]
set_property PACKAGE_PIN A13 [get_ports {threshold_discr_p_i[2]}]
set_property PACKAGE_PIN A14 [get_ports {threshold_discr_n_i[2]}]
set_property PACKAGE_PIN E13 [get_ports {threshold_discr_p_i[3]}]
set_property PACKAGE_PIN E14 [get_ports {threshold_discr_n_i[3]}]
set_property PACKAGE_PIN C13 [get_ports {threshold_discr_p_i[4]}]
set_property PACKAGE_PIN B13 [get_ports {threshold_discr_n_i[4]}]
set_property PACKAGE_PIN C14 [get_ports {threshold_discr_p_i[5]}]
set_property PACKAGE_PIN C15 [get_ports {threshold_discr_n_i[5]}]

## Miscellaneous I/O
set_property IOSTANDARD LVCMOS25 [get_ports clk_gen_rst]
set_property PACKAGE_PIN D19 [get_ports clk_gen_rst]
set_property IOSTANDARD LVCMOS25 [get_ports gpio]
set_property PACKAGE_PIN B16 [get_ports gpio]

## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN J19 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN H19 [get_ports sysclk_40_i_n]

## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_p]
set_property PACKAGE_PIN C18 [get_ports sysclk_50_o_p]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_n]
set_property PACKAGE_PIN C19 [get_ports sysclk_50_o_n]

## Inputs/Outputs for DUTs
set_property IOSTANDARD LVCMOS25 [get_ports {busy_o[*]}]
set_property PACKAGE_PIN L19 [get_ports {busy_o[0]}]
set_property PACKAGE_PIN K17 [get_ports {busy_o[1]}]
set_property PACKAGE_PIN J22 [get_ports {busy_o[2]}]
set_property PACKAGE_PIN L16 [get_ports {busy_o[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {triggers_o[*]}]
set_property PACKAGE_PIN M15 [get_ports {triggers_o[0]}]
set_property PACKAGE_PIN H20 [get_ports {triggers_o[1]}]
set_property PACKAGE_PIN K21 [get_ports {triggers_o[2]}]
set_property PACKAGE_PIN L14 [get_ports {triggers_o[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {cont_o[*]}]
set_property PACKAGE_PIN K18 [get_ports {cont_o[0]}]
set_property PACKAGE_PIN J20 [get_ports {cont_o[1]}]
set_property PACKAGE_PIN M18 [get_ports {cont_o[2]}]
set_property PACKAGE_PIN N18 [get_ports {cont_o[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {spare_o[*]}]
set_property PACKAGE_PIN N20 [get_ports {spare_o[0]}]
set_property PACKAGE_PIN M21 [get_ports {spare_o[1]}]
set_property PACKAGE_PIN N22 [get_ports {spare_o[2]}]
set_property PACKAGE_PIN M13 [get_ports {spare_o[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_o[*]}]
set_property PACKAGE_PIN G17 [get_ports {dut_clk_o[0]}]
set_property PACKAGE_PIN B17 [get_ports {dut_clk_o[1]}]
set_property PACKAGE_PIN D17 [get_ports {dut_clk_o[2]}]
set_property PACKAGE_PIN A18 [get_ports {dut_clk_o[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {cont_i[*]}]
set_property PACKAGE_PIN K19 [get_ports {cont_i[0]}]
set_property PACKAGE_PIN J21 [get_ports {cont_i[1]}]
set_property PACKAGE_PIN L18 [get_ports {cont_i[2]}]
set_property PACKAGE_PIN N19 [get_ports {cont_i[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {spare_i[*]}]
set_property PACKAGE_PIN M20 [get_ports {spare_i[0]}]
set_property PACKAGE_PIN L21 [get_ports {spare_i[1]}]
set_property PACKAGE_PIN M22 [get_ports {spare_i[2]}]
set_property PACKAGE_PIN L13 [get_ports {spare_i[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {triggers_i[*]}]
set_property PACKAGE_PIN M16 [get_ports {triggers_i[0]}]
set_property PACKAGE_PIN G20 [get_ports {triggers_i[1]}]
set_property PACKAGE_PIN K22 [get_ports {triggers_i[2]}]
set_property PACKAGE_PIN L15 [get_ports {triggers_i[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {busy_i[*]}]
set_property PACKAGE_PIN L20 [get_ports {busy_i[0]}]
set_property PACKAGE_PIN J17 [get_ports {busy_i[1]}]
set_property PACKAGE_PIN H22 [get_ports {busy_i[2]}]
set_property PACKAGE_PIN K16 [get_ports {busy_i[3]}]

set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_i[*]}]
set_property PACKAGE_PIN G18 [get_ports {dut_clk_i[0]}]
set_property PACKAGE_PIN B18 [get_ports {dut_clk_i[1]}]
set_property PACKAGE_PIN C17 [get_ports {dut_clk_i[2]}]
set_property PACKAGE_PIN A19 [get_ports {dut_clk_i[3]}]

# -------------------------------------------------------------------------------------------------


set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

# Clocks
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]

# sysclk is asynchronous to the oscillator 
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks osc_clk_100MHz] -group [get_clocks -include_generated_clocks sysclk_40_i_p]


# Tidy up timing report by putting in (bogus) constraints on trigger inputs
set_input_delay -clock [get_clocks s_clk320] -min 1.700 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -max 1.710 [get_ports {threshold_discr_p_i[*]}]

# Cycle is kept.
# N.B. Make sure timing relationship is correctly documented!
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {busy_i[*]}]

set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {dut_clk_i[*]}]

set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_sda_b]



