coarse_timestamp_o:OUTstd_logic_vector(g_COARSE_TIMESTAMP_WIDTH-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
);
...
@@ -134,8 +136,7 @@ ARCHITECTURE rtl OF eventFormatter IS
...
@@ -134,8 +136,7 @@ ARCHITECTURE rtl OF eventFormatter IS
signals_data_o:std_logic_vector(g_EVENT_DATA_WIDTH-1DOWNTO0);-- Multiplexed data from FIFOs
signals_data_o:std_logic_vector(g_EVENT_DATA_WIDTH-1DOWNTO0);-- Multiplexed data from FIFOs
constantc_COARSE_TIMESTAMP_WIDTH:positive:=48;-- ! Number of bits in 40MHz timestamp
--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
--!
--!
--!
--!
ENTITYlogic_clocksIS
entitylogic_clocksis
GENERIC(
generic(
g_USE_EXTERNAL_CLK:integer:=1
g_USE_EXTERNAL_CLK:integer:=1
);
);
PORT(
port(
ipbus_clk_i:INstd_logic;
ipbus_clk_i:instd_logic;
ipbus_i:INipb_wbus;
ipbus_i:inipb_wbus;
ipbus_reset_i:INstd_logic;
ipbus_reset_i:instd_logic;
Reset_i:INstd_logic;
Reset_i:instd_logic;
clk_logic_xtal_i:INstd_logic;--! 40MHz clock derived from onboard xtal
clk_logic_xtal_i:instd_logic;--! 40MHz clock derived from onboard xtal
clk_8x_logic_o:OUTstd_logic;--! 640MHz clock
clk_8x_logic_o:outstd_logic;--! 640MHz clock
clk_4x_logic_o:OUTstd_logic;--! 160MHz clock
clk_4x_logic_o:outstd_logic;--! 160MHz clock
ipbus_o:OUTipb_rbus;
ipbus_o:outipb_rbus;
strobe_8x_logic_o:OUTstd_logic;--! strobes once every 4 cycles of clk_16x
strobe_8x_logic_o:outstd_logic;--! strobes once every 4 cycles of clk_16x
strobe_4x_logic_o:OUTstd_logic;--! one pulse every 4 cycles of clk_4x
strobe_4x_logic_o:outstd_logic;--! one pulse every 4 cycles of clk_4x
DUT_clk_o:OUTstd_logic;--! 40MHz to DUTs
DUT_clk_o:outstd_logic;--! 40MHz to DUTs
logic_clocks_locked_o:OUTstd_logic;--! Goes high if clocks locked.
logic_clocks_locked_o:outstd_logic;--! Goes high if clocks locked.
logic_reset_o:OUTstd_logic--! Goes high to reset counters etc. Sync with clk_4x_logic
logic_reset_o:outstd_logic--! Goes high to reset counters etc. Sync with clk_4x_logic
);
);
-- Declarations
-- Declarations
ENDENTITYlogic_clocks;
endentitylogic_clocks;
--
--
ARCHITECTURErtlOFlogic_clocksIS
architecturertloflogic_clocksis
signals_clk40:std_logic;
signals_clk40:std_logic;
constantC_NUM_STROBE_TAPS:positive:=2;--! Adjust to shift strobes relative to 40MHz clock edge
constantC_NUM_STROBE_TAPS:positive:=2;--! Adjust to shift strobes relative to 40MHz clock edge
signals_clk40_delayed_160:std_logic_vector(C_NUM_STROBE_TAPSdownto0);--! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
signals_clk40_delayed_160:std_logic_vector(C_NUM_STROBE_TAPSdownto0);--! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
signals_clk40_delayed_320:std_logic_vector((2*C_NUM_STROBE_TAPS)+1downto0);--! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
signals_clk40_delayed_320:std_logic_vector((2*C_NUM_STROBE_TAPS)+1downto0);--! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
signals_clk160,s_clk160_internal:std_logic;
signals_clk160,s_clk160_internal:std_logic;
signals_clk320,s_clk320_internal:std_logic;
signals_clk320,s_clk320_internal:std_logic;
signals_locked_pll:std_logic;
signals_locked_pll:std_logic;
signals_clk:std_logic;
signals_clk:std_logic;
signals_DUT_Clk:std_logic;
signals_DUT_Clk:std_logic;
signals_clkfbout:std_logic;
signals_clkfbout:std_logic;
signals_logic_reset_ipb,s_logic_reset_ipb_d1:std_logic:='0';--! Reset signal in IPBus clock domain
signals_logic_reset_ipb,s_logic_reset_ipb_d1:std_logic:='0';--! Reset signal in IPBus clock domain
signals_logic_reset,s_logic_reset_d1,s_logic_reset_d2,s_logic_reset_d3,s_logic_reset_d4:std_logic:='0';--! reset signal clocked onto logic-clock domain.
signals_logic_reset,s_logic_reset_d1,s_logic_reset_d2,s_logic_reset_d3,s_logic_reset_d4:std_logic:='0';--! reset signal clocked onto logic-clock domain.
attributeSHREG_EXTRACT:string;
attributeSHREG_EXTRACT:string;
attributeSHREG_EXTRACTofs_logic_reset_d1:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d1:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d2:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d2:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d3:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d3:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d4:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_logic_reset_d4:signalis"no";-- Synchroniser not to be optimised into shreg
attributeSHREG_EXTRACTofs_clk40_delayed_160:signalis"no";-- delay to help timing not to be optimised into shreg
attributeSHREG_EXTRACTofs_clk40_delayed_160:signalis"no";-- delay to help timing not to be optimised into shreg
attributeSHREG_EXTRACTofs_clk40_delayed_320:signalis"no";-- delay to help timing not to be optimised into shreg
attributeSHREG_EXTRACTofs_clk40_delayed_320:signalis"no";-- delay to help timing not to be optimised into shreg
signals_ipbus_ack:std_logic:='0';
signals_ipbus_ack:std_logic:='0';
signals_reset_pll:std_logic:='0';-- ! PLL Reset signal
signals_reset_pll:std_logic:='0';-- ! PLL Reset signal
signals_clock_status_ipb:std_logic_vector(ipbus_o.ipb_rdata'range);--! contains status of clocks
signals_clock_status_ipb:std_logic_vector(ipbus_o.ipb_rdata'range);--! contains status of clocks
BEGIN
signals_enable_strobes:std_logic;-- take high to start strobes running.
g_NUM_COARSE_TS_BITS:natural:=3;--! Number of coarse ( clk_1x_logic normally 40MHz ) timestamp bits to add to MSB of trigger times.
g_IPBUS_WIDTH:positive:=32
g_IPBUS_WIDTH:positive:=32
);
);
PORT(
PORT(
...
@@ -94,6 +97,7 @@ ENTITY triggerInputs_newTLU IS
...
@@ -94,6 +97,7 @@ ENTITY triggerInputs_newTLU IS
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
reset_i:INstd_logic;
reset_i:INstd_logic;
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
...
@@ -127,13 +131,13 @@ ARCHITECTURE rtl OF triggerInputs_newTLU IS
...
@@ -127,13 +131,13 @@ ARCHITECTURE rtl OF triggerInputs_newTLU IS
signals_edge_falling_times:t_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! edge arrival time ( w.r.t. logic_strobe)
signals_edge_falling_times:t_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! edge arrival time ( w.r.t. logic_strobe)
signals_edge_rising:std_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! High when rising edge
signals_edge_rising:std_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! High when rising edge
signals_edge_falling:std_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! High when falling edge
signals_edge_falling:std_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! High when falling edge
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
signals_coarse_timestamp:std_logic_vector(c_TRIGIN_NUM_COARSE_TS_BITS-1downto0):=(others=>'0');-- counts on each strobe_4x_logic pulse
-- constant C_NUM_STROBE_TAPS : positive := 2; --! Adjust to shift strobes relative to 40MHz clock edge
-- signal s_clk40_delayed_160 : std_logic_vector(C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
-- signal s_clk40_delayed_320 : std_logic_vector((2*C_NUM_STROBE_TAPS)+1 downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
coarse_timestamp_o:outstd_logic_vector(g_COARSE_TIMESTAMP_WIDTH-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
);
...
@@ -320,7 +323,8 @@ architecture rtl of top is
...
@@ -320,7 +323,8 @@ architecture rtl of top is
----------------------------------------------
----------------------------------------------
COMPONENTtriggerInputs_newTLU
COMPONENTtriggerInputs_newTLU
GENERIC(
GENERIC(
g_NUM_INPUTS:natural:=1;
g_NUM_INPUTS:natural:=1;
g_NUM_COARSE_TS_BITS:natural:=3;--! Number of coarse ( clk_1x_logic normally 40MHz ) timestamp bits to add to MSB of trigger times.
g_IPBUS_WIDTH:positive:=32
g_IPBUS_WIDTH:positive:=32
);
);
PORT(
PORT(
...
@@ -332,6 +336,7 @@ architecture rtl of top is
...
@@ -332,6 +336,7 @@ architecture rtl of top is
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
reset_i:INstd_logic;
reset_i:INstd_logic;
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold