Commit 39db4b9c authored by David Cussans's avatar David Cussans

* Copying enclustra_ax3_pm3_infra.vhd from ipbus to fmc-mtlu-gw repo and

adding g_BUILD_SIMULATED_MAC generic to choose between physical and simulated Phy

* Modifying enclustra_ax3_pm3_infra.dep to pick up modified
enclustra_ax3_pm3_infra.vhd from  fmc-mtlu-gw repo rather than ipbus repo

* Removing unused ( and confusing ) top_enclustra_ax3_pm3.vhd

* Editing top_enclustra_tlu_v1e.vhd to pass downn g_BUILD_SIMULATED_MAC
parent fba19b1c
#-------------------------------------------------------------------------------
#
# Copyright 2017 - Rutherford Appleton Laboratory and University of Bristol
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# - - -
#
# Additional information about ipbus-firmare and the list of ipbus-firmware
# contacts are available at
#
# https://ipbus.web.cern.ch/ipbus
#
#-------------------------------------------------------------------------------
src enclustra_ax3_pm3_infra.vhd
src -c ipbus-firmware:components/ipbus_util clocks_7s_extphy_se.vhd ipbus_clock_div.vhd led_stretcher.vhd
include -c ipbus-firmware:components/ipbus_core
include -c ipbus-firmware:components/ipbus_eth artix_rgmii.dep
# Include simulated Ethernet - even though the Generate statement will ensure it never gets used.
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
---------------------------------------------------------------------------------
--
-- Copyright 2017 - Rutherford Appleton Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- enclustra_ax3_pm3_infra
--
-- All board-specific stuff goes here
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity enclustra_ax3_pm3_infra is
generic (
g_BUILD_SIMULATED_MAC :integer := 0 -- set != 0 to build with
-- simulated Phy
);
port(
sysclk: in std_logic; -- 50MHz board crystal clock
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
clk_200_o: out std_logic; -- needed to calibrate I/O delays
rst125_o: out std_logic;
clk_aux_o: out std_logic; -- 50MHz clock
rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end enclustra_ax3_pm3_infra;
architecture rtl of enclustra_ax3_pm3_infra is
signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_extphy_se
port map(
sysclk => sysclk,
clko_125 => clk125,
clko_125_90 => clk125_90,
clko_200 => clk200,
clko_ipb => clk_ipb_i,
locked => locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
clk_200_o <= clk200;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= (led_p(0), locked and onehz);
-- Ethernet MAC core and PHY interface
gen_ethernetPhy: if (g_BUILD_SIMULATED_MAC = 0) generate
-- Physical Phy
eth: entity work.eth_7s_rgmii
port map(
clk125 => clk125,
clk125_90 => clk125_90,
clk200 => clk200,
rst => rst125,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
else generate
-- Simulated Phy
eth: entity work.eth_mac_sim
generic map(
MULTI_PACKET => true
)
port map(
clk => clk125,
rst => rst125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
end generate gen_ethernetPhy;
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
-- Top-level design for ipbus demo
--
-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, 4/10/16--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library UNISIM;
--use UNISIM.vcomponents.all;
use work.ipbus.ALL;
entity top is
generic(
g_NUM_DUTS : positive := 3;
g_NUM_TRIG_INPUTS :positive := 4;
g_NUM_EXT_SLAVES :positive :=8;
g_EVENT_DATA_WIDTH :positive := 64;
g_IPBUS_WIDTH :positive := 32;
g_NUM_EDGE_INPUTS :positive := 4;
g_SPILL_COUNTER_WIDTH :positive := 12;
g_BUILD_SIMULATED_MAC :integer := 0
);
port(
sysclk: in std_logic;
leds: out std_logic_vector(3 downto 0); -- status LEDs
dip_sw: in std_logic_vector(3 downto 0); -- switches
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
i2c_scl_b: inout std_logic_vector(2 downto 0);
i2c_sda_b: inout std_logic_vector(2 downto 0);
phy_rstn: out std_logic; --default example ends here
busy_n_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
busy_p_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
cfd_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
cfd_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
gpio_hdr: out std_logic_vector(3 downto 0);
reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 1);
shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 1)
);
end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal inf_leds: std_logic_vector(1 downto 0);
SIGNAL s_i2c_scl_enb : std_logic_vector(2 downto 0);
SIGNAL s_i2c_sda_enb : std_logic_vector(2 downto 0);
--signal s_i2c_sda_i : std_logic;
--signal s_i2c_scl_i : std_logic;
begin
--led_iic_test <= iic_test;
--Implicit instantiation of output tristate buffers.
i2c_scl_b(0) <= '0' when (s_i2c_scl_enb(0) = '0') else 'Z';
i2c_sda_b(0) <= '0' when (s_i2c_sda_enb(0) = '0') else 'Z';
i2c_scl_b(1) <= '0' when (s_i2c_scl_enb(1) = '0') else 'Z';
i2c_sda_b(1) <= '0' when (s_i2c_sda_enb(1) = '0') else 'Z';
i2c_scl_b(2) <= '0' when (s_i2c_scl_enb(2) = '0') else 'Z';
i2c_sda_b(2) <= '0' when (s_i2c_sda_enb(2) = '0') else 'Z';
-- Infrastructure
infra: entity work.enclustra_ax3_pm3_infra
port map(
sysclk => sysclk,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
rst_125_o => phy_rst_e,
nuke => nuke,
soft_rst => soft_rst,
leds => inf_leds,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
mac_addr => mac_addr,
ip_addr => ip_addr,
ipb_in => ipb_in,
ipb_out => ipb_out
);
leds <= not ('0' & userled & inf_leds);
phy_rstn <= not phy_rst_e;
-- mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
-- ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
mac_addr <= X"020ddba1151f"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81f"; -- 192.168.200.16+n
-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
-- slaves: entity work.ipbus_example
-- port map(
-- ipb_clk => clk_ipb,
-- ipb_rst => rst_ipb,
-- ipb_in => ipb_out,
-- ipb_out => ipb_in,
-- nuke => nuke,
-- soft_rst => soft_rst,
-- i2c_scl_b => i2c_scl_b,
-- i2c_sda_b => i2c_sda_b,
-- userled => userled
-- );
--OBUFT: Single-ended 3-state Output Buffer
--7 Series
-- Xilinx HDL Libraries Guide, version 2012.2
--OBUFT_inst_scl : IOBUF
--generic map (
-- DRIVE => 12,
-- IOSTANDARD => "DEFAULT",
-- SLEW => "SLOW")
--port map (
-- IO => i2c_scl_b, -- Buffer output (connect directly to top-level port)
-- I => '0', -- Buffer input
-- T => s_i2c_scl_enb, -- 3-state enable input
-- O => s_i2c_scl_i
--); -- End of OBUFT_inst instantiation
--OBUFT_inst_sda : IOBUF
--generic map (
-- DRIVE => 12,
-- IOSTANDARD => "DEFAULT",
-- SLEW => "SLOW")
--port map (
-- IO => i2c_sda_b, -- Buffer output (connect directly to top-level port)
-- I => '0', -- Buffer input
-- T => s_i2c_sda_enb, -- 3-state enable input
-- O => s_i2c_sda_i
--); -- End of OBUFT_inst instantiation
slaves: entity work.ipbus_example
port map(
ipb_clk => clk_ipb,
ipb_rst => rst_ipb,
ipb_in => ipb_out,
ipb_out => ipb_in,
nuke => nuke,
soft_rst => soft_rst,
--i2c_scl_i => s_i2c_scl_i,
--i2c_sda_i => s_i2c_sda_i,
i2c_sda_i => i2c_sda_b,
i2c_scl_i => i2c_scl_b,
i2c_scl_enb_o => s_i2c_scl_enb,
i2c_sda_enb_o => s_i2c_sda_enb,
userled => userled
);
end rtl;
......@@ -5,7 +5,7 @@
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
include -c AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth --cd ../ucf enclustra_ax3_pm3.tcl
......
......@@ -460,6 +460,9 @@ begin
------------------------------------------
infra: entity work.enclustra_ax3_pm3_infra
generic map (
g_BUILD_SIMULATED_MAC => g_BUILD_SIMULATED_MAC
)
port map(
sysclk => clk_encl_buf,
clk_ipb_o => clk_ipb,
......
set_property FILE_TYPE {VHDL 2008} [get_files DUTInterface_AIDA_rtl.vhd]
set_property FILE_TYPE {VHDL 2008} [get_files enclustra_ax3_pm3_infra.vhd]
# ... or use this to set all files to VHDL 2008
# set_property file_type {VHDL 2008} [get_files [get_filesets sources_1]]
reorder_files -fileset constrs_1 -after [get_files enclustra_ax3_pm3.tcl] [get_files TLU_enclustra_v1e.xdc]
......
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