Skip to content

A
AIDA-2020 TLU - Gateware
Commit 6a8e8d29 authored by David Cussans's avatar David Cussans
Browse files
Options

* Modified build script build_tlu_firmware.sh to work with new OHWR repository names 

* Hacking on timing constraints in /TLU_enclustra_v1e.xdc
( added TCL command to set TLU_enclustra_v1e.xdc as "late" )
parent 70fd29ec
Hide whitespace changes
Inline Side-by-side
Showing with 61 additions and 31 deletions
AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep
View file @ 6a8e8d29
......@@ -15,5 +15,7 @@ src top_enclustra_tlu_v1e.vhd
src --cd ../ucf I2C_constr.xdc
src --cd ../ucf TLU_enclustra_v1e.xdc
setup --cd ../ucf TLU_enclustra_v1e_setProcessingOrder.xdc
#include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ 6a8e8d29
......@@ -130,39 +130,68 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
create_clock -period 6.250 -name s_clk160 -waveform {0.000 3.125} [get_pins I4/pll_base_inst/CLKOUT1]
create_clock -period 3.125 -name s_clk320 -waveform {0.000 1.562} [get_pins I4/pll_base_inst/CLKOUT0]
create_clock -period 32.000 -name clk_ipb_i -waveform {0.000 16.000} [get_pins infra/clocks/bufgipb/I]
##create_clock -period 6.250 -name s_clk160 -waveform {0.000 3.125} [get_pins I4/pll_base_inst/CLKOUT1]
##create_clock -period 3.125 -name s_clk320 -waveform {0.000 1.562} [get_pins I4/pll_base_inst/CLKOUT0]
##create_clock -period 32.000 -name clk_ipb_i -waveform {0.000 16.000} [get_pins infra/clocks/bufgipb/I]
# set_clock_groups -asynchronous -group [list [get_clocks sysclk]] -group [list [get_clocks sysclk_40_i_p]]
set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
##set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sysclk] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -clock_fall -min -add_delay 1.600 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -clock_fall -max -add_delay 1.850 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.200 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.100 [get_ports i2c_sda_b]
set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {cont_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {cont_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {dut_clk_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {dut_clk_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {spare_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {spare_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {triggers_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {triggers_o[*]}]
set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports gpio]
set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports gpio]
set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_sda_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_sda_b]
#set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {busy_i[*]}]
#set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {busy_i[*]}]
#set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {dut_clk_i[*]}]
#set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {dut_clk_i[*]}]
#set_input_delay -clock [get_clocks s_clk320] -clock_fall -min -add_delay 1.650 [get_ports {threshold_discr_p_i[*]}]
#set_input_delay -clock [get_clocks s_clk320] -clock_fall -max -add_delay 1.850 [get_ports {threshold_discr_p_i[*]}]
#set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_scl_b]
#set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.200 [get_ports i2c_scl_b]
#set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_sda_b]
#set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.100 [get_ports i2c_sda_b]
#set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {cont_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {cont_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {dut_clk_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {dut_clk_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {spare_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {spare_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {triggers_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {triggers_o[*]}]
#set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports gpio]
#set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports gpio]
#set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_scl_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_scl_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_sda_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_sda_b]
# Tidy up timing report by putting in (bogus) constraints on trigger inputs
set_input_delay -clock [get_clocks s_clk320] -min 1.70 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -max 1.71 [get_ports {threshold_discr_p_i[*]}]
# Cycle is kept.
# N.B. Make sure timing relationship is correctly documented!
set_input_delay -clock [get_clocks s_clk160] -min 3.2 [get_ports busy_i[*]]
set_input_delay -clock [get_clocks s_clk160] -max 3.3 [get_ports busy_i[*]]
set_input_delay -clock [get_clocks s_clk160] -min 3.2 [get_ports dut_clk_i[*]]
set_input_delay -clock [get_clocks s_clk160] -max 3.3 [get_ports dut_clk_i[*]]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_sda_b]
#
set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b]
set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_sda_b]
set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_sda_b]
# Ad-hoc hack
# set_false_path -from [get_pins infra/ipbus/trans/sm/hdr_reg[7]/C] -to [get_pins infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D]
set_false_path -from [get_pins {infra/ipbus/trans/sm/hdr_reg[7]/C}] -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
# set_false_path -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl 0 → 100644
View file @ 6a8e8d29
set_property PROCESSING_ORDER LATE [get_files TLU_enclustra_v1e.xdc]
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @ 6a8e8d29
#!/bin/sh
# Put which branch of Git to use here...
#IPBUS_BRANCH="-b enhancement/68"
#IPBUS_BRANCH="-b enhancement/28" # -- This one works, but now deleted...
IPBUS_BRANCH="-b v1.3"
TLU_BRANCH=""
......@@ -18,7 +16,7 @@ ipbb init build
cd build
ipbb add git https://github.com/ipbus/ipbus-firmware.git ${IPBUS_BRANCH}
ipbb add git git://ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git ${TLU_BRANCH}
ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git ${TLU_BRANCH}
# For read/write load a valid ssh key and use the repo below ....
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment