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AIDA-2020 TLU - Gateware
Commit 737d5bfc authored by David Cussans's avatar David Cussans
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Hacking around trying to fix problems with IPBus ( DUT interfaces not responding… 

Hacking around trying to fix problems with IPBus ( DUT interfaces not responding to IPBus , Shutter not responding to IPBus ).
Added rst_ipb signal to syncreg_v block in DUT interfaces and shutter. Added debug.

 Now operates "correctly". Will push to repo, remove debug and try again ( in case debug is accidentally squashing a timing issue ... )
parent 952bdb51
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Showing with 217 additions and 142 deletions
AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
View file @ 737d5bfc
......@@ -59,7 +59,8 @@ ENTITY T0_Shutter_Iface IS
ipbus_clk_i: in std_logic;
ipbus_i: in ipb_wbus;
ipbus_o: out ipb_rbus;
ipbus_reset_i: in std_logic; --! Synchronous with ipbus_clk_i
--! Output Signals
shutter_o: OUT STD_LOGIC; --! Shutter signal.
shutter_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers. NB. Should be *low* when shutters are disabled.
......@@ -121,7 +122,7 @@ begin
)
port map (
clk => ipbus_clk_i,
rst => reset_i,
rst => ipbus_reset_i,
ipb_in => ipbus_i,
ipb_out => ipbus_o,
slv_clk => clk_4x_i,
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ 737d5bfc
......@@ -6,10 +6,10 @@
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-------------------------------------------------------------------------------
-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
......@@ -25,6 +25,7 @@ USE ieee.std_logic_1164.all;
--!
--! @details
--
-- 13/March/19 - added ability to shift out trigger number.
ENTITY DUTInterface_AIDA IS
GENERIC(
......@@ -60,18 +61,18 @@ END ENTITY DUTInterface_AIDA ;
ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_strobe_4x_logic_d1 : std_logic;
signal s_dut_clk : std_logic := '0'; -- Clock to be sent to DUT connectors ( before final register )
signal s_dut_clk : std_logic := '0'; --! Clock to be sent to DUT connectors ( before final register )
signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal s_stretch_trig_in : std_logic := '0'; -- ! stretched version of trigger_i
signal s_stretch_trig_in : std_logic := '0'; --! stretched version of trigger_i
signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
signal s_trigger_out : std_logic := '0'; -- ! trigger shifted to start on strobe_4x_logic
-- Set length of output trigger here ( output length = length of this vector + 1 )
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
signal s_trigger_number_sr : std_logic_vector(g_NUM_TRIGNUM_BITS_TO_CLOCKOUT-1 downto 0);
signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0);
signal s_busy_clocking_trigger_number : std_logic;
signal s_trigger_number_sr : std_logic_vector(g_NUM_TRIGNUM_BITS_TO_CLOCKOUT-1 downto 0) := (others => '0'); --! Shift register loaded with trigger(event) number
signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0) := (others => '0'); --! Loaded with "ones" to indicate busy shifting trigger number
signal s_busy_clocking_trigger_number : std_logic := '0'; --! High when shifting trigger number
BEGIN
......@@ -84,21 +85,14 @@ BEGIN
if ( rising_edge(clk_4x_logic_i) and strobe_4x_logic_i = '1' ) then
if clockout_trigger_flag_i = '1' then -- if flag set then clock out trigger number
if (s_trigger_out_sr(0) = '1' and s_trigger_number_guard_sr(0) = '0') then -- If we have a trigger then load shift register with trigger number
if ( s_trigger_out = '1' and s_trigger_number_guard_sr(0) = '0' and clockout_trigger_flag_i = '1' ) then --! If we have a trigger, we are not busy with previous trigger and we want to shift out trigger number, then load shift register with trigger number
s_trigger_number_sr <= trigger_counter_i(s_trigger_number_sr'range);
s_trigger_number_guard_sr <= ( others =>'1');
else
s_trigger_number_sr <= '0' & s_trigger_number_sr(s_trigger_number_sr'left downto 1);
s_trigger_number_guard_sr <= '0' & s_trigger_number_guard_sr(s_trigger_number_guard_sr'left downto 1);
dut_reset_or_clk_o <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
end if;
else
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
end if;
end if;
end process p_dutClkRst;
......@@ -109,11 +103,10 @@ BEGIN
-- Optional generation of clock to DUT
gen_GenerateClock: if g_generate_clock generate
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
--! purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
--! should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
--! inputs : clk_4x_logic_i , strobe_4x_i
--! outputs: s_dut_clk
p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
begin -- process p_dut_clk_gen
if rising_edge(clk_4x_logic_i) then
......@@ -150,7 +143,7 @@ BEGIN
s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
end if;
--
--! Synchronize stretched trigger with strobe_4x_logic_i
if (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
s_trigger_out <= '1';
s_trigger_out_sr <= ( others => '1' );
......@@ -178,7 +171,14 @@ BEGIN
dut_clk_o <= s_dut_clk ;
dut_trigger_o <= s_trigger_out;
if clockout_trigger_flag_i = '1' then -- if flag set then clock out trigger number
dut_reset_or_clk_o <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
else
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
end if;
end if;
end process register_signals;
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
View file @ 737d5bfc
......@@ -130,6 +130,10 @@ ARCHITECTURE rtl OF DUTInterfaces IS
attribute mark_debug : string;
attribute mark_debug of s_IgnoreShutterVeto: signal is "true";
attribute mark_debug of s_DUT_ignore_busy: signal is "true";
attribute mark_debug of ipbus_reset_i: signal is "true";
attribute mark_debug of ipbus_i: signal is "true";
attribute mark_debug of ipbus_o: signal is "true";
BEGIN
......@@ -144,7 +148,8 @@ BEGIN
)
port map(
clk => ipbus_clk_i,
rst=> '0',--ipbus_reset_i ,
---rst=> '0',--ipbus_reset_i ,
rst => ipbus_reset_i,
ipb_in=> ipbus_i,
ipb_out=> ipbus_o,
slv_clk => clk_4x_logic_i,
......@@ -155,25 +160,6 @@ BEGIN
rstb => open
);
-- -- Synchronize registers from logic clock to ipbus.
-- sync_status: entity work.synchronizeRegisters
-- generic map (
-- g_NUM_REGISTERS => c_N_STAT )
-- port map (
-- clk_input_i => clk_4x_logic_i,
-- data_i => s_status_to_ipbus,
-- data_o => s_sync_status_to_ipbus,
-- clk_output_i => ipbus_clk_i);
-- -- Synchronize registers from logic clock to ipbus.
-- sync_ctrl: entity work.synchronizeRegisters
-- generic map (
-- g_NUM_REGISTERS => c_N_CTRL )
-- port map (
-- clk_input_i => ipbus_clk_i,
-- data_i => s_control_from_ipbus,
-- data_o => s_sync_control_from_ipbus,
-- clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
......@@ -192,93 +178,19 @@ BEGIN
s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
------------------------------------------------------------------------------
-- Instantiate BUFIODS
------------------------------------------------------------------------------
-- Loop through *all* DUTs ( including RJ45 )
dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
------------------------------------------------------------------
-- clk_IOBUFDS_inst : IOBUFDS
-- generic map (
-- IOSTANDARD => "BLVDS_25")
-- port map (
-- O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
-- IO => clk_to_dut_p_io(dut), --! Diff_p dut clock I/O (connect directly to top-level port)
-- IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
-- I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
-- T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
-- );
clk_to_dut(dut) <= s_clk_to_dut_aida(dut); -- do we need to disable this using T? No, the TLU now has enable signals.
s_clk_from_dut_eudet(dut) <= clk_from_dut(dut);
------------------------------------------------------------------
-- Now the signals are single ended: remove IBUFDS and use IBUF
-- busy_IBUFDS_inst : IBUFDS
-- generic map (
-- DIFF_TERM => TRUE, -- Differential Termination
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => s_busy_from_dut(dut), -- Buffer output
-- I => busy_from_dut_p_i(dut), -- Diff_p buffer input (connect directly to top-level port)
-- IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
-- );
-- busy_IBUF_inst : IBUF
-- generic map(
-- IBUF_LOW_PWR => TRUE,
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- O => s_busy_from_dut(dut),
-- I => busy_from_dut(dut)
-- );
s_busy_from_dut(dut) <= busy_from_dut(dut) ;
------------------------------------------------------------------
-- Connect internal signals to external
-- trig_OBUFDS_inst : OBUFDS
-- generic map (
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => trigger_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
-- OB => trigger_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
-- I => s_trigger_to_dut(dut) -- Buffer input
-- );
trigger_to_dut(dut) <= s_trigger_to_dut(dut);
------------------------------------------------------------------
-- clk_rst_OBUFDS_inst : OBUFDS
-- generic map (
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => reset_or_clk_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
-- OB => reset_or_clk_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
-- I => s_reset_or_clk_to_dut(dut) --s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut) -- Buffer input
-- );
reset_to_dut(dut) <= s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut);
end generate dut_clk_busy_trig_rst_io;
-- Loop through DUTs
dut_shutter_io: for dut in 0 to g_NUM_DUTS-1 generate
-- shutter_OBUFDS_inst : OBUFDS
-- generic map (
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
-- OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
-- I => s_shutter_to_dut(dut)
-- );
clk_to_dut <= s_clk_to_dut_aida;
s_clk_from_dut_eudet <= clk_from_dut;
shutter_to_dut(dut) <= s_shutter_to_dut(dut) ;
end generate dut_shutter_io;
s_busy_from_dut <= busy_from_dut ;
trigger_to_dut <= s_trigger_to_dut;
reset_to_dut <= s_reset_or_clk_to_dut and s_DUT_mask;
shutter_to_dut <= s_shutter_to_dut ;
------------------------------------------------------------------------------
-- Instantiate interfaces to DUTs
......@@ -323,7 +235,6 @@ BEGIN
system_clk_i => clk_4x_logic_i ,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i ,
-- ignore_shutter_veto_i => s_IgnoreShutterVeto ,
enable_dut_veto_i => s_dut_enable_veto_eudet(dut),
-- Connections to DUT:
dut_clk_i => s_clk_from_dut_eudet(dut),
......
AIDA_tlu/components/tlu/sim/hdl/DUTInterace_AIDA_tb.vhd 0 → 100644
View file @ 737d5bfc
-- Testbench created online at:
-- www.doulos.com/knowhow/perl/testbench_creation/
-- Copyright Doulos Ltd
-- SD, 03 November 2002
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
library ieee;
use ieee.math_real.all;
entity DUTInterface_AIDA_tb is
generic ( g_IPBUS_WIDTH : positive := 32 );
end;
architecture bench of DUTInterface_AIDA_tb is
component DUTInterface_AIDA
GENERIC(
g_IPBUS_WIDTH : positive := 32;
g_GENERATE_CLOCK : boolean := FALSE;
g_NUM_TRIGNUM_BITS_TO_CLOCKOUT : positive := 16;
g_NUM_TRIGNUM_GUARDBITS : positive := 4
);
PORT(
clk_4x_logic_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
clockout_trigger_flag_i : in std_logic;
trigger_i : IN std_logic;
reset_or_clk_to_dut_i : IN std_logic;
shutter_to_dut_i : IN std_logic;
busy_o : OUT std_logic;
dut_busy_i : IN std_logic;
dut_clk_o : OUT std_logic;
dut_reset_or_clk_o : OUT std_logic;
dut_shutter_o : OUT std_logic;
dut_trigger_o : OUT std_logic
);
end component;
signal clk_4x_logic_i: std_logic;
signal strobe_4x_logic_i: std_logic;
signal trigger_counter_i: std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0) := (others =>'0');
signal clockout_trigger_flag_i: std_logic;
signal trigger_i: std_logic := '0';
signal reset_or_clk_to_dut_i: std_logic := '0';
signal shutter_to_dut_i: std_logic := '0';
signal busy_o: std_logic;
signal dut_busy_i: std_logic := '0' ;
signal dut_clk_o: std_logic;
signal dut_reset_or_clk_o: std_logic;
signal dut_shutter_o: std_logic;
signal dut_trigger_o: std_logic ;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
signal s_strobe_counter : natural := 0; -- cycles through 0-3
signal s_cycle_counter, s_trigger_count : natural := 0; -- counts clock++
-- cycles and triggers
begin
uut: DUTInterface_AIDA generic map ( g_IPBUS_WIDTH => 32,
g_GENERATE_CLOCK => TRUE,
g_NUM_TRIGNUM_BITS_TO_CLOCKOUT => 16,
g_NUM_TRIGNUM_GUARDBITS => 4 )
port map ( clk_4x_logic_i => clk_4x_logic_i,
strobe_4x_logic_i => strobe_4x_logic_i,
trigger_counter_i => trigger_counter_i,
clockout_trigger_flag_i => clockout_trigger_flag_i,
trigger_i => trigger_i,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i,
busy_o => busy_o,
dut_busy_i => dut_busy_i,
dut_clk_o => dut_clk_o,
dut_reset_or_clk_o => dut_reset_or_clk_o,
dut_shutter_o => dut_shutter_o,
dut_trigger_o => dut_trigger_o );
stimulus: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 100.0; -- the range of random values created will be 0 to +100.
variable rand_time : time;
begin
-- Put initialisation code here
clockout_trigger_flag_i <= '1';
-- reset_i <= '1';
-- wait for clock_period*4;
-- reset_i <= '0';
-- Put test bench stimulus code here
for trig in 1 to 20 loop
uniform(seed1, seed2, rand); -- generate random number
rand_time := clock_period * (integer(rand*range_of_rand) + 20); -- rescale to 0..1000, convert integer part
wait for rand_time;
--wait for clock_period * 120;
-- pulse trigger_i for one cycle
wait until rising_edge(clk_4x_logic_i);
if (busy_o = '0' ) then
report "Injecting a pulse " & integer'image(trig) severity note;
trigger_i <= '1' ;
else
report "Pulse vetoed " & integer'image(trig) severity note;
trigger_i <= '0';
end if;
wait for clock_period * 2;
trigger_i <= '0';
s_trigger_count <= s_trigger_count + 1;
end loop; -- trig
-- Put test bench stimulus code here
wait for clock_period * 100;
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk_4x_logic_i <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
p_strobe: process (clk_4x_logic_i)
begin -- process p_strobe
if rising_edge(clk_4x_logic_i) then
s_cycle_counter <= (s_cycle_counter + 1 );
end if;
end process p_strobe;
trigger_counter_i <= std_logic_vector(to_unsigned(s_trigger_count , trigger_counter_i'length));
strobe_4x_logic_i <= '1' when (s_cycle_counter mod 4) = 0 else '0';
end;
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 737d5bfc
......@@ -25,7 +25,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000016"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000018"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -118,7 +118,7 @@ architecture rtl of top is
signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL logic_reset : std_logic;
SIGNAL logic_reset : std_logic := '0';
SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
SIGNAL overall_veto : std_logic; --! Halts triggers when high
SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
......@@ -188,9 +188,11 @@ architecture rtl of top is
);
PORT (
clk_4x_i : IN std_logic;
reset_i : IN std_logic;
clk_4x_strobe_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
T0_o : OUT std_logic;
run_active_o : out std_logic;
accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 DOWNTO 0);
......@@ -614,6 +616,7 @@ begin
I8 : T0_Shutter_Iface
PORT MAP (
clk_4x_i => clk_4x_logic,
reset_i => logic_reset,
clk_4x_strobe_i => strobe_4x_logic,
accelerator_signals_i => triggers,
T0_o => s_T0,
......@@ -622,7 +625,8 @@ begin
shutter_veto_o => s_shutter_veto,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_SHUTTER),
ipbus_o => ipbrr(N_SLV_SHUTTER)
ipbus_o => ipbrr(N_SLV_SHUTTER),
ipbus_reset_i => rst_ipb
);
------------------------------------------
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
View file @ 737d5bfc
......@@ -24,3 +24,4 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ 737d5bfc
......@@ -169,21 +169,21 @@ set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sysc
#set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_sda_b]
# Tidy up timing report by putting in (bogus) constraints on trigger inputs
set_input_delay -clock [get_clocks s_clk320] -min 1.70 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -max 1.71 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -min 1.700 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -max 1.710 [get_ports {threshold_discr_p_i[*]}]
# Cycle is kept.
# N.B. Make sure timing relationship is correctly documented!
set_input_delay -clock [get_clocks s_clk160] -min 3.2 [get_ports busy_i[*]]
set_input_delay -clock [get_clocks s_clk160] -max 3.3 [get_ports busy_i[*]]
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -min 3.2 [get_ports dut_clk_i[*]]
set_input_delay -clock [get_clocks s_clk160] -max 3.3 [get_ports dut_clk_i[*]]
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_sda_b]
#
#set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b]
......@@ -193,5 +193,10 @@ set_input_delay -clock [get_clocks clk_ipb_i] -max 17 [get_ports i2c_sda_b]
# Ad-hoc hack
# set_false_path -from [get_pins infra/ipbus/trans/sm/hdr_reg[7]/C] -to [get_pins infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D]
set_false_path -from [get_pins {infra/ipbus/trans/sm/hdr_reg[7]/C}] -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
# IPBus is intermittent with this set as a false path...
# set_false_path -from [get_pins {infra/ipbus/trans/sm/hdr_reg[7]/C}] -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
# set_false_path -to [get_pins {infra/ipbus/udp_if/clock_crossing_if/we_buf_reg[0]/D}]
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