Commit 92a25243 authored by David Cussans's avatar David Cussans

Bug fixes in simulation. Bug fix in fine-grain time-stamp

Inspection "by eye" shows linear correlation between delay of pulse and
fine-grain timestamp.
parent a590a053
......@@ -163,19 +163,10 @@ BEGIN
end process examine_lut;
--! Coarse time stamp. Phase w.r.t. strobe
-- c_coarse_ts : entity work.CounterUp
-- PORT MAP (
-- clk => clk_4x_logic_i,
-- ce => '1',
-- sinit => strobe_4x_logic_i, --'0',
-- q(31 downto 2) => open,
-- q(1 downto 0) => s_coarse_bits
-- );
--
c_coarse_ts : entity work.CounterWithReset
GENERIC MAP (
g_COUNTER_WIDTH => 2 )
g_COUNTER_WIDTH => 2,
g_OUTPUT_REGISTERS => 3)
PORT MAP (
clock_i => clk_4x_logic_i,
enable_i => '1',
......
......@@ -11,6 +11,9 @@ Point to input and output files on command line:
vsim -voptargs=+acc work.triggerinputs_newtlu_tb(bench) -G g_BFMINPUT="/users/phdgc/tlu-tmp-2020-2-24/work/build/proj/triggerInputs_sim/BFM_INPUT_01.txt" -G g_BFMOUTPUT="/users/phdgc/tlu-tmp-2020-2-24/work/build/proj/triggerInputs_sim/BFM_OUTPUT_01.txt"
... or just
vsim work.triggerinputs_newtlu_tb -G g_BFMINPUT=BFM_INPUT_01.txt -G g_BFMOUTPUT=BFM_OUTPUT_01.txt
Reads from input file
cmd arg1 arg2 ....
......
......@@ -5,7 +5,7 @@
@boardname = "enclustra_ax3_pm3"
src -c AIDA_tlu/components/tlu ../../sim/hdl/triggerInputs_newTLU_tb.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu ../../sim/hdl/triggerInputs_newTLU_tb.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu ../../sim/hdl/transactionGenerator_behavioural.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu ../../sim/hdl/ipbusTransactor_behavioural.vhd
......
......@@ -75,7 +75,9 @@ architecture bench of triggerInputs_newTLU_tb is
signal s_pulseTransaction : t_pulseTransaction;
signal s_pulseTransactionReturn : t_pulseTransactionReturn;
signal s_pulse_sync : std_logic := '0'; -- strobe high once every 8 clock cycles of 40MHz
constant delta : time := 0.02 ns; -- make sure IPBus clock drifts w.r.t.
-- logic clocks
constant clockLogic_period : time := 25 ns; -- 40MHz clock
......@@ -114,6 +116,10 @@ begin
clk_8x_logic_i => clk_8x_logic_i,
strobe_8x_logic_i => strobe_8x_logic_i);
proc_PrintTimes: process (trigger_times_o) is
begin -- process proc_PrintTimes
report "Got a trigger time" & " " & to_hstring(trigger_times_o(0)) & " " & to_hstring(trigger_times_o(1)) & " "& to_hstring(trigger_times_o(2)) & " "& to_hstring(trigger_times_o(3)) & " "& to_hstring(trigger_times_o(4)) & " "& to_hstring(trigger_times_o(5)) severity note;
end process proc_PrintTimes;
stimSequence : process
begin
......@@ -149,11 +155,14 @@ begin
);
s_pulse_sync <= '1' when strobe_4x_logic_i='1' and s_coarse_timestamp = "000" and rising_edge(strobe_4x_logic_i) else '0';
pulseGen: entity work.variablePulseTransactor
generic map (
g_BUSWIDTH => g_IPBUS_WIDTH) -- width for triggernumber and timestamp
port map (
clk_i => strobe_4x_logic_i,
--clk_i => strobe_4x_logic_i,
clk_i => s_pulse_sync,
trans_i => s_pulseTransaction,
returnedData_o => s_pulseTransactionReturn,
signal_o => s_pulses,
......
......@@ -60,7 +60,7 @@ begin -- rtl
v_lastEdge := (v_pulseDelay + v_pulseWidth);
end if;
if trans_i(chan).r_delay > 0 then
if trans_i(chan).r_delay >= 0 then
report "Queing pulse . chan , delay , width " & integer'image(chan) & " " & time'image(v_pulseDelay) & " " & time'image(v_pulseWidth);
signal_o(chan) <= '1' after v_pulseDelay, '0' after (v_pulseDelay + v_pulseWidth);
else
......@@ -70,6 +70,7 @@ begin -- rtl
end loop;
report "Waiting until last edge finished. Delay = " & time'image(v_lastEdge) severity note;
wait for v_lastEdge;
-- Update trigger number
......
#!/usr/bin/python
#
# script to generate input for triggerinputs_newtlu_tb
#
print "777 Generate test pulses in 200ps steps"
print "2 8000"
for i in range(1000):
print "3 " + str( i * 2) + " 3000 -10 0 -10 0 -10 0 -10 0 -10 0"
print "2 3000"
print "2 8000"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment