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AIDA-2020 TLU - Gateware
Commit a6d98f22 authored by David Cussans's avatar David Cussans
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* DUTInterfaces* modified to be able to clock out trigger number in AIDA mode 

* Stretch FIFO reset in eventBuffer_rtl.vhd

* Incremented version number ( to 16 ) in top_enclustra_tlu_v1e.vhd

* Added a few lines to TLU_enclustra_v1e_setProcessingOrder.tcl to force processing order of XDC file and set VHDL type to 2008 on one file...
parent e3a38fdd
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AIDA_tlu/components/tlu/firmware/hdl/SyncGenerator_rtl.vhd
View file @ a6d98f22
......@@ -156,7 +156,7 @@ BEGIN
s_truncated_counter_value <= unsigned( s_counter_value( s_truncated_counter_value'range));
--! Process to drive s_counter_lt_t1 , s_counter_lt_t2, s_counter_lt_t3
p_comparators: PROCESS (clock_i)
p_comparators: PROCESS (clock_i,strobe_i)
BEGIN
IF rising_edge(clock_i) and (strobe_i='1') THEN
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ a6d98f22
......@@ -28,18 +28,19 @@ USE ieee.std_logic_1164.all;
ENTITY DUTInterface_AIDA IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
g_IPBUS_WIDTH : positive := 32;
g_GENERATE_CLOCK : boolean := FALSE; --! Set true to generate a clock to DUT in logic ( rather than using clock generated in clock generator chip )
g_NUM_TRIGNUM_BITS_TO_CLOCKOUT : positive := 16;
g_NUM_TRIGNUM_GUARDBITS : positive := 4
);
PORT(
clk_4x_logic_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
clockout_trigger_flag_i : in std_logic; --! Set high to clock out trigger counter on rst/dut-clock line
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. Gets passed to DUT pins
-- ignore_shutter_veto_i : in std_logic;
ignore_dut_busy_i : in std_logic;
--dut_mask_i : in std_logic; --! Set high if DUT is active. Moved one level up
busy_o : OUT std_logic; --! goes high when DUT is busy or vetoed by shutter
-- Signals to/from DUT
......@@ -68,32 +69,69 @@ ARCHITECTURE rtl OF DUTInterface_AIDA IS
-- Set length of output trigger here ( output length = length of this vector + 1 )
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
signal s_trigger_number_sr : std_logic_vector(g_NUM_TRIGNUM_BITS_TO_CLOCKOUT-1 downto 0);
signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0);
signal s_busy_clocking_trigger_number : std_logic;
BEGIN
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
dut_shutter_o <= shutter_to_dut_i;
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- purpose: drives dut_reset_or_clk_o
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
begin -- process p_dut_clk_gen
if rising_edge(clk_4x_logic_i) then
if (strobe_4x_logic_i = '1') then
s_dut_clk <= '1';
s_dut_clk_sr <= "001";
-- inputs : clk_4x_logic_i
p_dutClkRst: process (clk_4x_logic_i ) is
begin -- process p_dutClkRst
if ( rising_edge(clk_4x_logic_i) and strobe_4x_logic_i = '1' ) then
if clockout_trigger_flag_i = '1' then -- if flag set then clock out trigger number
if (s_trigger_out_sr(0) = '1' and s_trigger_number_guard_sr(0) = '0') then -- If we have a trigger then load shift register with trigger number
s_trigger_number_sr <= trigger_counter_i(s_trigger_number_sr'range);
s_trigger_number_guard_sr <= ( others =>'1');
else
s_trigger_number_sr <= '0' & s_trigger_number_sr(s_trigger_number_sr'left downto 1);
s_trigger_number_guard_sr <= '0' & s_trigger_number_guard_sr(s_trigger_number_guard_sr'left downto 1);
dut_reset_or_clk_o <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
end if;
else
s_dut_clk <= s_dut_clk_sr(0);
s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
end if;
end if;
end process p_dut_clk_gen;
end process p_dutClkRst;
s_busy_clocking_trigger_number <= s_trigger_number_guard_sr(0);
dut_shutter_o <= shutter_to_dut_i;
-- Optional generation of clock to DUT
gen_GenerateClock: if g_generate_clock generate
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
begin -- process p_dut_clk_gen
if rising_edge(clk_4x_logic_i) then
if (strobe_4x_logic_i = '1') then
s_dut_clk <= '1';
s_dut_clk_sr <= "001";
else
s_dut_clk <= s_dut_clk_sr(0);
s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);
end if;
end if;
end process p_dut_clk_gen;
else generate
s_dut_clk <= '0'; -- Set clock to zero and rely on external clock generator chip
end generate;
-- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic
-- type : combinational
......@@ -135,15 +173,10 @@ BEGIN
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
-- ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( (dut_busy_i and DUT_mask_i ) );
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( dut_busy_i );
busy_o <= dut_busy_i;
busy_o <= dut_busy_i or s_busy_clocking_trigger_number;
dut_clk_o <= s_dut_clk ;
--dut_trigger_o <= DUT_mask_i and s_trigger_out;
dut_trigger_o <= s_trigger_out;
end if;
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_EUDET_rtl.vhd
View file @ a6d98f22
......@@ -125,7 +125,7 @@ end process;
-- DUT clock and setting shift_reg_ce for one cycle of system_clk_i when
-- the DUT clock rising edge comes by.
if (shift_reg_ce ='1' ) then
trig_shift_reg <= '0' & trig_shift_reg(g_TRIGGER_DATA_WIDTH-1 downto 1);
trig_shift_reg <= '0' & trig_shift_reg(trig_shift_reg'left downto 1);
serial_trig_data <= trig_shift_reg(0);
-- otherwise load shift register if we have just had a trigger.
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
View file @ a6d98f22
......@@ -38,7 +38,7 @@ use unisim.VComponents.all;
--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) ,2=reserved ,3= AIDA mode with trigger number clocked out on RESET line
--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
--! \li 0x00000008 - DUT mask ( read )
--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
......@@ -75,15 +75,8 @@ ENTITY DUTInterfaces IS
clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
trigger_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
--clk_to_dut_n_io : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! clocks trigger data when in EUDET mode
--clk_to_dut_p_io : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! clocks trigger data when in EUDET mode
--reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Either reset line or trigger
--reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Either reset line or trigger
reset_to_dut: OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Replaces reset_or_clk_to_dut
--trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
--trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Shutter output. Output 0 (RJ45) has no shutter signal
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Shutter output
shutter_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Shutter output
veto_o : OUT std_logic --! goes high when one or more DUT are busy or vetoed by shutter
);
......@@ -114,6 +107,8 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit to 1 for AIDA mode, 0 for EUDET
signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
signal s_aida_clockout_trigger_flag : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Set high to clock out trigger number in AIDA mode.
signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');
signal s_IgnoreShutterVeto : std_logic := '0'; -- --! When high the shutter won't veto triggers when low.
......@@ -298,13 +293,11 @@ BEGIN
PORT map (
clk_4x_logic_i => clk_4x_logic_i ,
strobe_4x_logic_i => strobe_4x_logic_i ,
trigger_counter_i => trigger_counter_i ,
trigger_counter_i => trigger_counter_i ,
clockout_trigger_flag_i => s_aida_clockout_trigger_flag(dut),
trigger_i => trigger_i ,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i ,
-- ignore_shutter_veto_i => s_IgnoreShutterVeto ,
ignore_dut_busy_i => s_DUT_ignore_busy(dut),
--dut_mask_i => s_DUT_mask(dut),
busy_o => s_dut_veto_aida(dut),
-- Signals to/from DUT
......@@ -340,8 +333,11 @@ BEGIN
);
s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
s_aida_clockout_trigger_flag(dut) <= s_DUT_interface_mode( (2*dut) + 1 );
s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
-- Produce "OR" of veto/busy signals from DUTs, take into account IGNORE BUSY bit
s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or ( s_dut_veto(dut) and (not s_DUT_ignore_busy(dut) ) );
......
AIDA_tlu/components/tlu/firmware/hdl/eventBuffer_rtl.vhd
View file @ a6d98f22
......@@ -52,10 +52,10 @@ ENTITY eventBuffer IS
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic --! reset buffers when high. Synch withclk_4x_logic
);
-- Declarations
......@@ -75,6 +75,9 @@ ARCHITECTURE rtl OF eventBuffer IS
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
signal s_ack : std_logic := '0'; -- -- IPBus ACK signal
constant c_NUM_RESET_CYCLES : positive := 16; --! Number of cycles to stretch reset pulses
signal s_rst_fifo_ipb_sr, s_rst_fifo_clk4x_sr : std_logic_vector(c_NUM_RESET_CYCLES-1 downto 0); -- ! shift registers to stretch reset pulses
COMPONENT tlu_event_fifo
PORT (
rst : IN STD_LOGIC;
......@@ -136,8 +139,39 @@ BEGIN
end if;
end process ipbus_write;
rst_fifo_o <= s_rst_fifo_ipb;
s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
-- Pulse stretcher for reset pulse on IPBus clock
p_ipbusclk_reset: process (ipbus_clk_i) is
begin -- process p_ipbusclk_reset
if rising_edge(ipbus_clk_i) then
if s_rst_fifo_ipb = '1' then
s_rst_fifo_ipb_sr <= (others => '1');
else
s_rst_fifo_ipb_sr <= '0' & s_rst_fifo_ipb_sr(s_rst_fifo_ipb_sr'left downto 1);
end if;
s_rst_fifo <= s_rst_fifo_ipb_sr(0) or s_rst_fifo_ipb or s_rst_fifo_clk4x_sr(0);
rst_fifo_o <= s_rst_fifo;
end if;
end process p_ipbusclk_reset;
-- Pulse stretcher for reset pulse on clk4x ( 160MHz clock )
p_clk4x_reset: process (clk_4x_logic_i) is
begin -- process p_clk4x_reset
if rising_edge(clk_4x_logic_i) then
if logic_reset_i = '1' then
s_rst_fifo_clk4x_sr <= (others => '1');
else
s_rst_fifo_clk4x_sr <= '0' & s_rst_fifo_clk4x_sr(s_rst_fifo_clk4x_sr'left downto 1);
end if;
end if;
end process p_clk4x_reset;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
......
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ a6d98f22
......@@ -25,7 +25,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000015"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000016"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl
View file @ a6d98f22
set_property FILE_TYPE {VHDL 2008} [get_files DUTInterface_AIDA_rtl.vhd]
reorder_files -fileset constrs_1 -after enclustra_ax3_pm3.tcl TLU_enclustra_v1e.xdc
set_property PROCESSING_ORDER LATE [get_files TLU_enclustra_v1e.xdc]
exit
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