Commit b61af01c authored by David Cussans's avatar David Cussans

Changed triggerInput test bench to use logic_clocks entity.

This led to some minor changes to logic_clocks. Hopefully making it more robust...
parent def38894
......@@ -64,10 +64,14 @@ architecture bench of triggerInputs_newTLU_tb is
signal s_clk40_delayed_160 : std_logic_vector(C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
signal s_clk40_delayed_320 : std_logic_vector((2*C_NUM_STROBE_TAPS)+1 downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
constant clock320_period: time := 3.125 ns; -- 320 MHz clock
constant clock200_period: time := 5 ns; -- 200 MHz clock
signal s_dut_clk, s_clocks_locked , s_logic_reset : std_logic;
constant delta : time := 0.02 ns; -- make sure IPBus clock drifts w.r.t.
-- logic clocks
constant clockLogic_period : time := 25 ns; -- 40MHz clock
--constant clock320_period: time := 3.125 ns; -- 320 MHz clock
constant clock200_period: time := 5 ns + delta; -- 200 MHz clock
constant clockipbus_period: time := 31.25 ns + delta; -- 320 MHz clock
signal stop_the_clock: boolean;
......@@ -82,7 +86,7 @@ begin
strobe_4x_logic_i => strobe_4x_logic_i,
threshold_discr_p_i => threshold_discr_p_i,
threshold_discr_n_i => threshold_discr_n_i,
reset_i => reset_i,
reset_i => s_logic_reset,
trigger_times_o => trigger_times_o,
trigger_o => trigger_o,
edge_rising_times_o => edge_rising_times_o,
......@@ -101,59 +105,47 @@ begin
stop_the_clock <= false;
-- Put initialisation code here
reset_i <= '1';
wait for clock320_period * 16;
ipbus_reset_i <= '1';
wait for clockLogic_period * 16;
reset_i <= '0';
wait for clock320_period * 200;
ipbus_reset_i <= '0';
wait for clockLogic_period * 500;
-- Put test bench stimulus code here
stop_the_clock <= true;
wait;
stop_the_clock <= true;
reset_i <= '1';
wait;
end process;
clock320: process
clockGenerator: ENTITY work.logic_clocks
port map (
ipbus_clk_i => ipbus_clk_i,
ipbus_i => ipbus_i,
ipbus_reset_i => ipbus_reset_i,
Reset_i => reset_i,
clk_logic_xtal_i => clk_logic,
clk_8x_logic_o => clk_8x_logic_i,
clk_4x_logic_o => clk_4x_logic,
ipbus_o => ipbus_o,
strobe_8x_logic_o => strobe_8x_logic_i,
strobe_4x_logic_o => strobe_4x_logic_i,
DUT_clk_o => s_dut_clk,
logic_clocks_locked_o => s_clocks_locked,
logic_reset_o => s_logic_reset
);
clockLogic: process
begin
while not stop_the_clock loop
clk_8x_logic_i <= '0', '1' after clock320_period / 2;
wait for clock320_period;
clk_logic <= '0', '1' after clockLogic_period / 2;
wait for clockLogic_period;
end loop;
wait;
end process;
clock4x_1x: process( clk_8x_logic_i )
variable ctr : unsigned(2 downto 0):= (others => '0');
begin
if rising_edge( clk_8x_logic_i ) then
clk_4x_logic <= not clk_4x_logic;
ctr := ctr + 1;
clk_logic <= ctr(2);
end if;
end process;
-- Generate a strobe signal for 160MHz clock
generate_4x_strobe: process (clk_4x_logic, clk_logic)
begin -- process generate_4x_strobe
if rising_edge(clk_4x_logic) then
s_clk40_delayed_160 <= s_clk40_delayed_160(s_clk40_delayed_160'left-1 downto 0) & clk_logic;
strobe_4x_logic_i <= s_clk40_delayed_160(s_clk40_delayed_160'left-1) and not s_clk40_delayed_160(s_clk40_delayed_160'left);
end if;
end process generate_4x_strobe;
-- Generate a strobe signal for 320MHz clock
generate_8x_strobe: process (clk_8x_logic_i, clk_logic)
begin -- process generate_4x_strobe
if rising_edge(clk_8x_logic_i) then
s_clk40_delayed_320 <= s_clk40_delayed_320(s_clk40_delayed_320'left-1 downto 0) & clk_logic;
strobe_8x_logic_i <= s_clk40_delayed_320(s_clk40_delayed_320'left-1) and not s_clk40_delayed_320(s_clk40_delayed_320'left);
end if;
end process generate_8x_strobe;
clockIpbus: process
begin
while not stop_the_clock loop
......
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