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AIDA-2020 TLU - Gateware
Commit cad3311b authored by David Cussans's avatar David Cussans
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Working on getting TLU simulation to work 

triggerLogic_rtl.vhd - changed not to need VHDL-2008
tlu_1e.dep - changed to correct order to work with ipbb sim. Added VHDL-2008 flags
top_tim.dep - top level dep file to build simulation
infra_sim.vhd - infrastructure ( Ethernet Mac + IPBus control ) for simulation. IPBB not able to ignore synthesis only files
parent ae0fe926
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AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerLogic_rtl.vhd
View file @ cad3311b
......@@ -90,7 +90,9 @@ ARCHITECTURE rtl OF triggerLogic IS
signal s_internal_trigger, s_internal_trigger_d : std_logic := '0'; -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
-- signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation
signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation and counter delay
signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0'; -- ! Goes high when internal trigger is running.
signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0'; --! Goes high when internal trigger is running.
signal s_load_internal_trigger_counter : std_logic := '0'; --! Goes high to load counter counts down to generate regular internal triggers
-- signal s_logic_reset , s_logic_reset_ipb : std_logic := '0'; -- ! Take high to reset counters etc.
signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0'; -- ! Can't read from an output port so keep internal copy
......@@ -112,8 +114,8 @@ ARCHITECTURE rtl OF triggerLogic IS
constant c_N_STAT : positive := 16;
signal s_controlRegStrobes : std_logic_vector(c_N_CTRL-1 downto 0) := ( others => '0') ; --!
--Bit strobes when control reg is loaded
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0):= ( others => ( others => '0'));
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0):= ( others => ( others => '0'));
signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_loadTriggerPattern , s_loadTriggerPattern_p1 : std_logic := '0'; -- take high to load trigger pattern
......@@ -310,15 +312,16 @@ BEGIN
s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" )) else '0';
s_load_internal_trigger_counter <= s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d);
-- Use a coregen counter to allow timing constraints to be met.
--c_internal_triggers: entity work.internalTriggerGenerator
c_internal_triggers: internalTriggerGenerator
PORT MAP (
clk => clk_4x_logic_i,
ce => s_internal_trigger_active,
load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
load => s_load_internal_trigger_counter,
l => s_internal_trigger_interval,
q => s_internal_trigger_timer
);
......
AIDA_tlu/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
View file @ cad3311b
......@@ -11,29 +11,26 @@ src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
src -c AIDA_tlu/components/tlu fmcTLU_pkg.vhd
src -c AIDA_tlu/components/tlu fmcTLU_pkg_body.vhd
src -c AIDA_tlu/components/tlu eventBuffer_rtl.vhd
src -c AIDA_tlu/components/tlu logic_clocks_rtl.vhd
src -c AIDA_tlu/components/tlu trigger/triggerInputs_newTLU_rtl.vhd
src -c AIDA_tlu/components/tlu eventFormatter_rtl.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu eventFormatter_rtl.vhd
src -c AIDA_tlu/components/tlu T0_Shutter_Iface_rtl.vhd
src -c AIDA_tlu/components/tlu SyncGenerator_rtl.vhd
src -c AIDA_tlu/components/tlu counterWithResetPreset_rtl.vhd
src -c AIDA_tlu/components/tlu counterDownGated_rtl.vhd
src -c AIDA_tlu/components/tlu delayPulse4x_rtl.vhd
# src -c AIDA_tlu/components/tlu delayPulse4x_rtl.vhd
src -c AIDA_tlu/components/tlu stretchPulse4x_rtl.vhd
src -c AIDA_tlu/components/tlu dut/DUTInterfaces_rtl.vhd
src -c AIDA_tlu/components/tlu dut/DUTInterface_AIDA_rtl.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu dut/DUTInterface_AIDA_rtl.vhd
src -c AIDA_tlu/components/tlu dut/DUTInterface_EUDET_rtl.vhd
src -c AIDA_tlu/components/tlu trigger/triggerLogic_rtl.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu trigger/triggerLogic_rtl.vhd
src -c AIDA_tlu/components/tlu synchronizeRegisters_rtl.vhd
src -c AIDA_tlu/components/tlu trigger/arrivalTimeLUT_rtl.vhd
src -c AIDA_tlu/components/tlu counterWithReset_rtl.vhd
src -c AIDA_tlu/components/tlu trigger/dualSERDES_1to4_rtl.vhd
src --vhdl2008 -c AIDA_tlu/components/tlu trigger/dualSERDES_1to4_rtl.vhd
src -c AIDA_tlu/components/tlu trigger/IODELAYCal_FSM_rtl.vhd
src -c AIDA_tlu/components/tlu pulseClockDomainCrossing_rtl.vhd
src -c AIDA_tlu/components/tlu single_pulse_rtl.vhd
......@@ -45,16 +42,19 @@ src -c AIDA_tlu/projects/TLU_v1e ipbus_decode_TLUaddrmap.vhd
# Include I2C AIDA_tlu/components
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_rtl.vhd
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_top.vhd
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_bit_ctrl.vhd
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_byte_ctrl.vhd
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_registers.vhd
src -c AIDA_tlu/components/external/opencores_i2c i2c_master_rtl.vhd
# Inclide IP ( *.xci files )
# Include IP ( *.xci files )
src -c AIDA_tlu/components/tlu --cd ../cgn tlu_event_fifo.xci
src -c AIDA_tlu/components/tlu --cd ../cgn internalTriggerGenerator.xci
# Include type definitions for TLU
src -c AIDA_tlu/components/tlu fmcTLU_pkg_body.vhd
src -c AIDA_tlu/components/tlu fmcTLU_pkg.vhd
AIDA_tlu/projects/sim/firmware/cfg/top_sim.dep
View file @ cad3311b
......@@ -23,7 +23,35 @@
#
#-------------------------------------------------------------------------------
@device_family = "artix7"
@device_name = "xc7a35t"
@device_package = "csg324"
@device_speed = "-2"
@boardname = "enclustra_ax3_pm3"
src top_sim.vhd
include -c AIDA_tlu/projects/TLU_v1e top_tlu_1e_a35.dep
src -c AIDA_tlu/projects/TLU_v1e top_enclustra_tlu_v1e.vhd
src -c AIDA_tlu/projects/sim --vhdl2008 infra_sim.vhd
src -c ipbus-firmware:components/ipbus_util clocks_7s_extphy_se.vhd led_stretcher.vhd ipbus_clock_div.vhd
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
#
include -c AIDA_tlu/projects/TLU_v1e tlu_1e.dep
include -c ipbus-firmware:components/ipbus_core
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
include -c ipbus-firmware:components/ipbus_slaves syncreg_v.dep
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
AIDA_tlu/projects/sim/firmware/hdl/infra_sim.vhd 0 → 100644
View file @ cad3311b
---------------------------------------------------------------------------------
--
-- Copyright 2017 - Rutherford Appleton Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- enclustra_ax3_pm3_infra
--
-- All board-specific stuff goes here
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity enclustra_ax3_pm3_infra is
generic (
g_BUILD_SIMULATED_MAC :integer := 0 -- set != 0 to build with
-- simulated Phy
);
port(
sysclk: in std_logic; -- 50MHz board crystal clock
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
clk_200_o: out std_logic; -- needed to calibrate I/O delays
rst125_o: out std_logic;
clk_aux_o: out std_logic; -- 50MHz clock
rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end enclustra_ax3_pm3_infra;
architecture rtl of enclustra_ax3_pm3_infra is
signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_extphy_se
port map(
sysclk => sysclk,
clko_125 => clk125,
clko_125_90 => clk125_90,
clko_200 => clk200,
clko_ipb => clk_ipb_i,
locked => locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
clk_200_o <= clk200;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= (led_p(0), locked and onehz);
-- Ethernet MAC core and PHY interface
-- Simulated Phy
eth: entity work.eth_mac_sim
generic map(
MULTI_PACKET => true
)
port map(
clk => clk125,
rst => rst125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
AIDA_tlu/projects/sim/firmware/hdl/top_sim.vhd
View file @ cad3311b
......@@ -75,23 +75,23 @@ architecture bench of top_tb is
signal rgmii_rxd: std_logic_vector(3 downto 0);
signal rgmii_rx_ctl: std_logic;
signal rgmii_rxc: std_logic;
signal phy_rstn: std_logic;
signal phy_rstn: std_logic ;
signal i2c_scl_b: std_logic;
signal i2c_sda_b: std_logic;
signal i2c_reset: std_logic;
signal clk_gen_rst: std_logic;
signal busy_i: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal busy_i: std_logic_vector(g_NUM_DUTS-1 downto 0):= (others => '0');
signal busy_o: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal cont_i: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal cont_i: std_logic_vector(g_NUM_DUTS-1 downto 0):= (others => '0');
signal cont_o: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal spare_i: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal spare_i: std_logic_vector(g_NUM_DUTS-1 downto 0):= (others => '0');
signal spare_o: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal triggers_i: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal triggers_i: std_logic_vector(g_NUM_DUTS-1 downto 0):= (others => '0');
signal triggers_o: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal dut_clk_i: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal dut_clk_i: std_logic_vector(g_NUM_DUTS-1 downto 0):= (others => '0');
signal dut_clk_o: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal threshold_discr_n_i: std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
signal threshold_discr_p_i: std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0) ;
signal threshold_discr_n_i: std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0) := (others => '1');
signal threshold_discr_p_i: std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0) := (others => '0');
-- Simulate mis-match between nominal 50MHz clock freq and actual freq
constant freqDrift: time := 0.01 ns;
......
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