Commit dd0b9f42 authored by David Cussans's avatar David Cussans

Bug fixes to allow synthesis. Adding trigger number to test bench

parent 92a25243
......@@ -93,7 +93,7 @@ ENTITY eventFormatter IS
ipbus_o : OUT ipb_rbus;
data_strobe_o : OUT std_logic; --! goes high when data ready to load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
coarse_timestamp_o : OUT std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
coarse_timestamp_o : OUT std_logic_vector (g_COARSE_TIMESTAMP_WIDTH-1 DOWNTO 0); --! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i : IN std_logic; --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o : OUT std_logic --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
......
......@@ -77,7 +77,8 @@ architecture bench of triggerInputs_newTLU_tb is
signal s_pulseTransactionReturn : t_pulseTransactionReturn;
signal s_pulse_sync : std_logic := '0'; -- strobe high once every 8 clock cycles of 40MHz
signal s_triggerNumber : std_logic_vector(g_IPBUS_WIDTH - 1 downto 0);
constant delta : time := 0.02 ns; -- make sure IPBus clock drifts w.r.t.
-- logic clocks
constant clockLogic_period : time := 25 ns; -- 40MHz clock
......@@ -116,9 +117,11 @@ begin
clk_8x_logic_i => clk_8x_logic_i,
strobe_8x_logic_i => strobe_8x_logic_i);
proc_PrintTimes: process (trigger_times_o) is
proc_PrintTimes: process (trigger_o) is
begin -- process proc_PrintTimes
report "Got a trigger time" & " " & to_hstring(trigger_times_o(0)) & " " & to_hstring(trigger_times_o(1)) & " "& to_hstring(trigger_times_o(2)) & " "& to_hstring(trigger_times_o(3)) & " "& to_hstring(trigger_times_o(4)) & " "& to_hstring(trigger_times_o(5)) severity note;
if rising_edge(trigger_o(0)) or rising_edge(trigger_o(1)) then
report "Got a trigger time " & to_hstring(s_triggerNumber) & " " & time'image(NOW) & " " & to_hstring(trigger_times_o(0)) & " " & to_hstring(trigger_times_o(1)) & " "& to_hstring(trigger_times_o(2)) & " "& to_hstring(trigger_times_o(3)) & " "& to_hstring(trigger_times_o(4)) & " "& to_hstring(trigger_times_o(5)) severity note;
end if;
end process proc_PrintTimes;
stimSequence : process
begin
......@@ -166,7 +169,7 @@ begin
trans_i => s_pulseTransaction,
returnedData_o => s_pulseTransactionReturn,
signal_o => s_pulses,
triggerNumber_o => open,
triggerNumber_o => s_triggerNumber,
timeStamp_o => open
);
......
......@@ -290,7 +290,7 @@ architecture rtl of top is
ipbus_o : OUT ipb_rbus ;
data_strobe_o : OUT std_logic ; --! goes high when data ready TO load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
coarse_timestamp_o : out std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
coarse_timestamp_o : out std_logic_vector (g_COARSE_TIMESTAMP_WIDTH-1 DOWNTO 0); --! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i : IN std_logic ; --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o : OUT std_logic --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
......
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