Commit dfc56e11 authored by David Cussans's avatar David Cussans

Removing commented out code

parent d5da54ef
......@@ -120,24 +120,7 @@ BEGIN
);
-----------------------------------------------------
-- iodelay_prompt : delayIO
-- port map
-- (
-- data_in_from_pins_p(0) => data_i_pos,
-- data_in_from_pins_n(0) => data_i_neg,
-- data_in_to_device(0) => s_Data_i_d_p,
-- delay_clk => fabricClk_i,
-- in_delay_reset => '0',
-- in_delay_data_ce(0) => '1',
-- in_delay_data_inc(0) => '0',
-- delay_locked => open,
-- ref_clock => fabricClk_i,
-- clk_in => fastClk_i,
-- clock_enable => '1',
-- io_reset => s_rst_cal
-- );
prompt_val <= "00000";
IDELAY2_Prompt : IDELAYE2
......@@ -163,57 +146,9 @@ BEGIN
);
----IODELAY2 no longer valid. Replaced using IP delay (SelectIO interface wizard generated)
-- IODELAY2_Prompt : IODELAY2
-- generic map (
-- COUNTER_WRAPAROUND => "STAY_AT_LIMIT" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
-- DATA_RATE => "SDR", -- "SDR" or "DDR"
-- DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
-- SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
-- IDELAY_TYPE => "VARIABLE_FROM_ZERO",
-- IDELAY_VALUE => 0 -- Amount of taps for fixed input delay (0-255)
-- --SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
-- )
-- port map (
-- BUSY => s_busy_idelay_p, -- 1-bit output: Busy output after CAL
-- DATAOUT => s_Data_i_d_p, -- 1-bit output: Delayed data output to ISERDES/input register
-- DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
-- DOUT => open, -- 1-bit output: Delayed data output
-- TOUT => open, -- 1-bit output: Delayed 3-state output
-- CAL => s_cal, -- 1-bit input: Initiate calibration input
-- CE => '0', -- 1-bit input: Enable INC input
-- CLK => fabricClk_i, -- 1-bit input: Clock input
-- IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
-- INC => '0', -- 1-bit input: Increment / decrement input
-- IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
-- IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
-- ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
-- RST => s_rst_cal, -- 1-bit input: reset_i to 1/2 of total delay period
-- T => '1' -- 1-bit input: 3-state input signal
-- );
s_busy_idelay_p <= (prompt_val(0) XOR prompt_out(0)) OR (prompt_val(1) XOR prompt_out(1)) OR (prompt_val(2) XOR prompt_out(2)) OR (prompt_val(3) XOR prompt_out(3)) OR (prompt_val(4) XOR prompt_out(4));
status_o(1) <= s_busy_idelay_p;
-- iodelay_delay : delayIO
-- port map
-- (
-- data_in_from_pins_p(0) => data_i_pos,
-- data_in_from_pins_n(0) => data_i_neg,
-- data_in_to_device(0) => s_Data_i_d_d,
-- delay_clk => fabricClk_i,
-- in_delay_reset => '0',
-- in_delay_data_ce(0) => '1',
-- in_delay_data_inc(0) => '0',
-- delay_locked => open,
-- ref_clock => fabricClk_i,
-- clk_in => fastClk_i,
-- clock_enable => '1',
-- clk_out => open,
-- io_reset => s_rst_cal
-- );
-- This should be configurable via IPBus. For now fixed value. The tap value is 200 MHz (5 ns). We want
-- a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 6 taps.
......@@ -244,36 +179,6 @@ BEGIN
);
-- IODELAY2_Delayed : IODELAY2
-- generic map (
-- COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
-- DATA_RATE => "SDR", -- "SDR" or "DDR"
-- DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
-- SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
-- IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
-- IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
-- IDELAY2_VALUE => 0 -- Delay value when IDELAY_MODE="PCI" (0-255)
-- --SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
-- )
-- port map (
-- BUSY => s_busy_idelay_d, -- 1-bit output: Busy output after CAL
-- DATAOUT => s_Data_i_d_d, -- 1-bit output: Delayed data output to ISERDES/input register
-- DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
-- DOUT => open, -- 1-bit output: Delayed data output
-- TOUT => open, -- 1-bit output: Delayed 3-state output
-- CAL => s_cal, -- 1-bit input: Initiate calibration input
-- CE => '0', -- 1-bit input: Enable INC input
-- CLK => fabricClk_i, -- 1-bit input: Clock input
-- IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
-- INC => '0', -- 1-bit input: Increment / decrement input
-- IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
-- IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
-- ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
-- RST => s_rst_cal, -- 1-bit input: reset_i to zero
-- T => '1' -- 1-bit input: 3-state input signal
-- );
--I must check that the CNTVALUEOUT and CNTVALUEIN are the same. TO DO
--status_o(0) <= s_busy_idelay_d;
s_busy_idelay_d <= (delay_val(0) XOR delayed_out(0)) OR (delay_val(1) XOR delayed_out(1)) OR (delay_val(2) XOR delayed_out(2)) OR (delay_val(3) XOR delayed_out(3)) OR (delay_val(4) XOR delayed_out(4));
......@@ -281,35 +186,6 @@ BEGIN
s_busy <= s_busy_idelay_p or s_busy_idelay_d;
-----------------------------------------------------
--ISERDES2 replaced by ISERDESE2 in Series 7
-- ISERDES2_Prompt : ISERDES2
-- generic map (
-- BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
-- DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
-- DATA_WIDTH => 4, -- Parallel data width selection (2-8)
-- INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
-- SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
-- )
-- port map (
-- -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
-- Q1 => s_Data_o(1), -- Oldest data
-- Q2 => s_Data_o(3),
-- Q3 => s_Data_o(5),
-- Q4 => s_Data_o(7), -- most recent data
-- --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
-- VALID => open, -- 1-bit output Output status of the phase detector
-- BITSLIP => '0', -- 1-bit input Bitslip enable input
-- CE0 => '1', -- 1-bit input Clock enable input
-- CLK0 => fastClk_i, -- 1-bit input I/O clock network input
-- CLK1 => '0', -- 1-bit input Secondary I/O clock network input
-- CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
-- D => s_Data_i_d_p, -- 1-bit input Input data
-- IOCE => strobe_i, -- 1-bit input Data strobe_i input
-- RST => reset_i, -- 1-bit input Asynchronous reset_i input
-- SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
-- );
ISERDESE2_Prompt: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
generic map (
DATA_RATE => "DDR",
......@@ -345,33 +221,7 @@ BEGIN
OFB=> '0'
);
-- ISERDES2_Delayed : ISERDES2
-- generic map (
-- BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
-- DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
-- DATA_WIDTH => 4, -- Parallel data width selection (2-8)
-- INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
-- SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
-- )
-- port map (
-- -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
-- Q1 => s_Data_o(0), -- oldest data
-- Q2 => s_Data_o(2),
-- Q3 => s_Data_o(4),
-- Q4 => s_Data_o(6), -- most recent data
-- --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
-- VALID => open, -- 1-bit output Output status of the phase detector
-- BITSLIP => '0', -- 1-bit input Bitslip enable input
-- CE0 => '1', -- 1-bit input Clock enable input
-- CLK0 => fastClk_i, -- 1-bit input I/O clock network input
-- CLK1 => '0', -- 1-bit input Secondary I/O clock network input
-- CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
-- D => s_Data_i_d_d, -- 1-bit input Input data
-- IOCE => strobe_i, -- 1-bit input Data strobe_i input
-- RST => reset_i, -- 1-bit input Asynchronous reset_i input
-- SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
-- );
ISERDESE2_Delayed: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
generic map (
......
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