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AIDA-2020 TLU - Gateware
Commit f66918f5 authored by David Cussans's avatar David Cussans
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Bug fixes in simulation. Bug fixes in rising/falling edge swap 

generate_bfm_input - text fed into HREAD must be long enough to fill variable ( e.g. HREAD into 32 bit integer needs 8 chars )

dualSERDES_1to_4 - changed delay on delayed IDELAYE2 in order to balance up delays
triggerInputs_newTLU - fixed bug in code to swap between rising and falling edges

TLUaddrmap.xml - added new register for optional invert edge selection.

transactionGenerator_behavioural.vhd - simulation should now finish cleanly, rather than hanging in loop
parent dd0b9f42
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Showing with 59 additions and 15 deletions
AIDA_tlu/components/tlu/firmware/hdl/trigger/dualSERDES_1to4_rtl.vhd
View file @ f66918f5
......@@ -150,9 +150,9 @@ BEGIN
status_o(1) <= s_busy_idelay_p;
-- This should be configurable via IPBus. For now fixed value. The tap value is 200 MHz (5 ns). We want
-- a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 6 taps.
delay_val <= "00110";
-- This should be configurable via IPBus. For now fixed value. The tap value at 200 MHz (5
-- ns) is 78ps . We want a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 10 taps.
delay_val <= "01010";
--delay_val <= "00000";
IDELAY2_Delayed : IDELAYE2
......
AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl.vhd
View file @ f66918f5
......@@ -37,6 +37,7 @@ use unisim.vcomponents.all;
--!
--! @details
--! \li IPBus address 0 = control and status
--! \li write -->
--! \li bit0 = reset serdes
--! \li bit1 = reset counter
--! \li bit2 = calibrate IDELAYs
......@@ -71,6 +72,7 @@ use unisim.vcomponents.all;
--! \li IPBus address 3 = edge rising(2) counter
--! \li IPBus address 4 = edge rising(3) counter
--!
--! \li Address 1 = invert input bits 5..0. Set 1 to select for negative going pulses.
--!
--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
--! Author:
......@@ -129,13 +131,13 @@ ARCHITECTURE rtl OF triggerInputs_newTLU IS
signal s_edge_falling_times: t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
signal s_edge_rising: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge
signal s_edge_falling: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when falling edge
constant c_N_CTRL : positive := 1;
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
-- signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
signal s_select_input_invert : std_logic_vector(g_NUM_INPUTS-1 downto 0) := ( others => '1'); -- set bit high to invert input
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
......@@ -145,6 +147,7 @@ BEGIN
-- by synchronizer.
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map (
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT )
port map(
clk=> ipbus_clk_i,
......@@ -181,7 +184,8 @@ BEGIN
s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
s_counter_reset <= s_sync_control_from_ipbus(0)(1);
s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
s_select_input_invert <= s_sync_control_from_ipbus(1)(g_NUM_INPUTS-1 downto 0);
s_status_to_ipbus(0)(0) <= s_rst_iserdes;
s_status_to_ipbus(0)(1) <= s_counter_reset;
s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
......@@ -267,7 +271,8 @@ BEGIN
s_edge_rising_times(triggerInput) <= coarse_timestamp_i & s_edge_rising_time_short;
s_edge_falling_times(triggerInput) <= coarse_timestamp_i & s_edge_falling_time_short;
-- purpose: registers output of arrivalTimeLUT and performs optional edge
-- purpose: registers output of arrivalTimeLUT and performs optional
-- edge inversion
proc_registerLUT_output : process (clk_4x_logic) is
begin -- process proc_registerLUT_output
......@@ -278,7 +283,6 @@ BEGIN
-- In the future have this selectable.
edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
if (s_edge_rising(triggerInput) = '1') then
trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
end if;
......@@ -287,7 +291,20 @@ BEGIN
edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
end if;
trigger_o(triggerInput) <= s_edge_rising(triggerInput);
-- If s_select_input_invert(triggerInput) = 0 then connect up
-- rising edge. Otherwise falling edge.
if s_select_input_invert(triggerInput) = '0' then
trigger_o(triggerInput) <= s_edge_rising(triggerInput);
if (s_edge_rising(triggerInput) = '1') then
trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
end if;
else
trigger_o(triggerInput) <= s_edge_falling(triggerInput);
if (s_edge_falling(triggerInput) = '1') then
trigger_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
end if;
end if;
end if;
end process proc_registerLUT_output;
......
AIDA_tlu/components/tlu/sim/hdl/transactionGenerator_behavioural.vhd
View file @ f66918f5
......@@ -28,7 +28,11 @@ use std.TEXTIO.all;
--
--! @details
--! Must be compiled with VHDL-2008 ( uses HREAD and HWRITE ).
--!
--! \li Pause = 2 [delay]
--! \li Pulse (delay,width in 100ps ticks) = 3 [delay before pulse] [width]
--! \li IPBus transaction = 0 [ipbus params]
--! \li IPBus write = 0 0 [addr] [data]
--! \li IPBus read = 0 1 [addr] [dummy]
--! <b>Dependencies:</b>\n
--! None
--!
......@@ -41,6 +45,7 @@ use std.TEXTIO.all;
--! \n\n<b>Last changes:</b>\n
--! 9/March/2012 DGC - changing address and data to be STD_LOGIC_VECTOR. \n
--! using HWRITE / HREAD for Hexidecimal IO
--! 1/March/2020 DGC - repurposed for AIDA-2020 TLU work. Changed syntax
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
......
AIDA_tlu/components/tlu/sim/hdl/triggerInputs_newTLU_tb.vhd
View file @ f66918f5
......@@ -76,6 +76,9 @@ architecture bench of triggerInputs_newTLU_tb is
signal s_pulseTransaction : t_pulseTransaction;
signal s_pulseTransactionReturn : t_pulseTransactionReturn;
signal s_wbTransaction : t_wbTransaction;
signal s_wbTransactionReturn : t_wbTransactionReturn;
signal s_pulse_sync : std_logic := '0'; -- strobe high once every 8 clock cycles of 40MHz
signal s_triggerNumber : std_logic_vector(g_IPBUS_WIDTH - 1 downto 0);
......@@ -147,9 +150,8 @@ begin
BFMOUTPUT => g_BFMOUTPUT --! Output file
)
port map (
wb_transaction_o => open, -- ! signal that carries transaction to
-- IPBus interface
wb_returned_data_i => c_wbNullTransactionReturn, -- ! Carrys data back from BFM
wb_transaction_o => s_wbTransaction, -- ! signal that carries transaction to IPBus transactor
wb_returned_data_i => s_wbTransactionReturn, -- ! Carrys data back from BFM
pulse_transaction_o => s_pulseTransaction,
pulse_returned_data_i => s_pulseTransactionReturn,
......@@ -176,6 +178,17 @@ begin
threshold_discr_p_i <= s_pulses;
threshold_discr_n_i <= not s_pulses;
ipbusGen : entity work.ipbusTransactor
port map (
-- interface to transaction generator
Trans => s_wbTransaction,
returnedData => s_wbTransactionReturn,
-- interface to "physical" ports
clk_i => ipbus_clk_i,
ipb_to_slave => ipbus_i, --! Signals from master to slave
ipb_from_slave => ipbus_o --! Signals from slave to master
);
clockGenerator : entity work.logic_clocks
port map (
ipbus_clk_i => ipbus_clk_i,
......@@ -233,7 +246,7 @@ begin
end if;
s_coarse_timestamp <= std_logic_vector(v_tsctr);
end loop;
wait;
end process;
end;
......
AIDA_tlu/components/tlu/sim/scripts/generate_bfm_input.py
View file @ f66918f5
......@@ -3,8 +3,16 @@
# script to generate input for triggerinputs_newtlu_tb
#
print "777 Generate test pulses in 200ps steps"
# waiting for clocks to settle
print "2 8000"
# setting up trigger inputs to look for falling edges
print "0 0 00006001 FFFFFFFF"
#
# generate pulses
for i in range(1000):
print "3 " + str( i * 2) + " 3000 -10 0 -10 0 -10 0 -10 0 -10 0"
# pause between pulses
print "2 3000"
# pause before ending simulation
print "2 8000"
AIDA_tlu/projects/TLU_v1e/addr_table/TLUaddrmap.xml
View file @ f66918f5
......@@ -50,7 +50,8 @@
</node>
<!-- This needs checking. The counters work, not sure about the reset -->
<node id="triggerInputs" address="0x6000" description="Inputs configuration" fwinfo="endpoint;width=4">
<node id="SerdesRstW" address="0x0" permission="w" description="" />
<node id="SerdesRstW" address="0x0" permission="w" description="" />
<node id="InvertEdgeW" address="0x1" permission="w" description="Set bit high to invert sense of leading edge" />
<node id="SerdesRstR" address="0x8" permission="r" description="" />
<node id="ThrCount0R" address="0x9" permission="r" description="" />
<node id="ThrCount1R" address="0xa" permission="r" description="" />
......
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