Skip to content

A
AIDA-2020 TLU - Gateware
Commit fc4ec402 authored by David Cussans's avatar David Cussans
Browse files
Options

Tidying up whilst sorting out simulation. 

deleting pc051a_infra_sim.{dep,vhd} - these files were never needed
deleting enclustra_ax3_pm3_infra.patch - made a copy, so don't need to patch
deleting enclustra_ax3_pm3_infra.vhd - duplicate copy
parent cad3311b
Hide whitespace changes
Inline Side-by-side
Showing with 0 additions and 253 deletions
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_infra_sim.dep deleted 100644 → 0
View file @ cad3311b
src pc051a_infra_sim.vhd
src -c ipbus-firmware:components/ipbus_util ../sim_hdl/clock_sim_7s.vhd
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
include -c ipbus-firmware:components/ipbus_core
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/pc051a_infra_sim.vhd deleted 100644 → 0
View file @ cad3311b
-- kc705_basex_infra
--
-- All board-specific stuff goes here.
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity pc051a_infra_sim is
port(
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
rst125_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end pc051a_infra_sim;
architecture rtl of pc051a_infra_sim is
signal clk125_fr, clk125, clk_ipb, clk_ipb_i, rst125, rst_ipb, rst_ipb_ctrl: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clock_sim_7s
port map(
clko_125 => clk125,
clko_ipb => clk_ipb_i,
locked => open,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
-- Ethernet MAC core and PHY interface
eth: entity work.eth_mac_sim
generic map(
MULTI_PACKET => true
)
port map(
clk => clk125,
rst => rst125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr
);
end rtl;
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.patch deleted 100644 → 0
View file @ cad3311b
--- enclustra_ax3_pm3_infra.vhd 2019-01-23 14:06:26.356312145 +0000
+++ enclustra_ax3_pm3_infra.vhd.new 2019-01-23 14:07:31.598717626 +0000
@@ -41,6 +41,7 @@
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
+ clk_200_o: out std_logic;
rst125_o: out std_logic;
clk_aux_o: out std_logic; -- 50MHz clock
rst_aux_o: out std_logic;
@@ -93,6 +94,7 @@
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
+ clk_200_o <= clk200;
stretch: entity work.led_stretcher
generic map(
AIDA_tlu/components/tlu/firmware/hdl/enclustra_ax3_pm3_infra.vhd deleted 100644 → 0
View file @ cad3311b
-- enclustra_ax3_pm3_infra
--
-- All board-specific stuff goes here
--
-- Dave Newbold, June 2013---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity enclustra_ax3_pm3_infra is
port(
sysclk: in std_logic; -- ??? board crystal clock
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
rst_125_o: out std_logic;
clk_200_o: out std_logic;
--clk_aux_o: out std_logic; -- 40MHz generated clock
--rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end enclustra_ax3_pm3_infra;
architecture rtl of enclustra_ax3_pm3_infra is
signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_extphy_se
port map(
sysclk => sysclk,
clko_125 => clk125,
clko_125_90 => clk125_90,
clko_200 => clk200,
clko_ipb => clk_ipb_i,
locked => locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
rst_125_o <= rst125;
clk_200_o <= clk200;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= (led_p(0), locked and onehz);
-- Ethernet MAC core and PHY interface
eth: entity work.eth_7s_rgmii
port map(
clk125 => clk125,
clk125_90 => clk125_90,
clk200 => clk200,
rst => rst125,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment