Was seeing behaviour in hardware not seen in simulation. Put in reset circuitry to AIDA DUT interface. Added one extra register for clk4x (160MHz) outputs.

TODO:

• Sort out timing constraints ( Vivado wasn't reporting negative slack even though design didn't work )
• Produce new config. file for Si5345 that moves the DUT clocks 10ns later. (abandoned - changed phase of 160MHz, 320MHz strobes w.r.t. incoming clock instead. DGC, 27/Apr/19 ).