- Sort by
- Name
- Oldest updated
- Last updated
-
1e000015 Tidied up timing constraints. May help with problems seen at DESY with 1e000014
Changes w.r.t. 1e000014:
Tidied up timing constraints
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000019 Added ability to clock out trigger number in AIDA (synchronous) handshake mode
Added ability to clock out trigger number in AIDA (synchronous) handshake mode
In MaskMode , which is four 2-bit flags, one for each DUT the available modes are as follows: 00 = EUDET ( trigger/busy handshake. Optional clock out of trigger number by DUT transmitting a clock) 01 = AIDA with trigger number ( trigger number clocked out on edge of clock transmitted to DUT) 11 = AIDA without trigger number
In EUDAQ, setting DUTMaskMode in AIDA TLU *.conf file controls the DUT interface mode. For example:
- DUTMaskMode = 0x00 sets all DUT interfaces to EUDAQ ( trigger/busy )
- DUTMaskMode = 0x55 sets all DUT outputs to AIDA mode with trigger number
- DUTMaskMode = 0xFF sets all DUT outputs to AIDA mode.
- DUTMaskMode = 0xD3 sets DUTs 0,3 to AIDA without trigger number, DUT 2 to AIDA with trigger number and DUT 1 to EUDAQ
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000020 Was seeing behaviour in hardware not seen in simulation. Put in reset circuitry to AIDA DUT interface. Added one extra register for clk4x (160MHz) outputs.
Was seeing behaviour in hardware not seen in simulation. Put in reset circuitry to AIDA DUT interface. Added one extra register for clk4x (160MHz) outputs.
TODO:
- Sort out timing constraints ( Vivado wasn't reporting negative slack even though design didn't work )
- Produce new config. file for Si5345 that moves the DUT clocks 10ns later. (abandoned - changed phase of 160MHz, 320MHz strobes w.r.t. incoming clock instead. DGC, 27/Apr/19 ).
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000022 Fixes to 1e000020 Added registers to give reset and trigger lines same relationship with clock in AIDA+trigger-num mode Builds (at least once... ) to give bitstream who's behaviour matches simulation
Fixes to 0d7cb8ca
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000024 Modifications to clocking: Edited logic_clocks.vhd to generate strobes for 320MHz and 160MHz clock domains from 40MHz clock supplied by PLL ( not shift register ). Should be more robust. Data signals ( Trigger , Sync/T0 ) still delayed by ~ 3ns with respect to Si5345 clock on DUT cables ( see https://webapps-pp.bris.ac.uk/elog/AIDA/105 )
Modifications to clocking:
Edited logic_clocks.vhd to generate strobes for 320MHz and 160MHz clock domains from 40MHz clock supplied by PLL ( not shift register ). Should be more robust.
Data signals ( Trigger , Sync/T0 ) still delayed by ~ 3ns with respect to Si5345 clock on DUT cables ( see https://webapps-pp.bris.ac.uk/elog/AIDA/105 )
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000025 * With selectable polarity pulses . * Improved test-bench ( BFM from Maroc ) * Builds against IPBus v1.6
- With selectable polarity pulses .
- Improved test-bench ( BFM from Maroc )
- Builds against IPBus v1.6
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar
-
1e000026 Should be exactly the same as 1e000025 , but with bug in build script fixed.
- Source code
- Download zip
- Download tar.gz
- Download tar.bz2
- Download tar