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AIDA-2020 TLU - Hardware
Commit 0de2161e authored by David Cussans's avatar David Cussans
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Checked artwork for new quote. Exported body centre placement information

parent 03b259ec
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Showing with 64651 additions and 35707 deletions
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/.rtcomp
View file @ 0de2161e
Total: 218 Missing: 0
Total etch: 102.14
Total vias: 91
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/README
View file @ 0de2161e
......@@ -13,7 +13,7 @@ contact: David.Cussans@bristol.ac.uk
tel: 0117 928 7481
Files produced by Cadence Allegro PE16.6
Files produced by Cadence Allegro PE17.2
Artwork:
--------
......@@ -24,7 +24,7 @@ All layers viewed from top
Build:
------
Six Layers as follows:
Four Layers as follows:
fmc_tlu_leds_pmt_pwr_L01.art
fmc_tlu_leds_pmt_pwr_L02.art
......@@ -85,7 +85,7 @@ Drill information ( Excellon format, described in nc_param.txt )
-----------------
Plated and unplated holes in same file.
fmc_tlu_leds_pmt_pwr_24-1-4.drl
fmc_tlu_leds_pmt_pwr_31-1-4.drl
Bill of Materials
......@@ -107,4 +107,4 @@ placement_pin1.txt
ODB++ format (PCB and assembly information):
-------------
fmc_tlu_leds_pmt_pwr_24.tgz
fmc_tlu_leds_pmt_pwr_31.tgz
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/allegro.jrl
View file @ 0de2161e
\t (00:00:05) allegro 17.2 S028 Linux SPB 64-bit Edition
\t (00:00:05) Journal start - Thu Feb 8 16:25:59 2018
\t (00:00:05) Host=fortis.phy.bris.ac.uk User=phpgb Pid=25880 CPUs=4
\t (00:00:05) CmdLine= /software/CAD/Cadence/SPB172/tools/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_leds_pmt_pwr.cpm -product Allegro_performance -option Allegro_PCB_HighSpeed_Option -option Allegro_PCB_Mini_Option -mpssession phpgb_ProjectMgr28183 -mpshost fortis.phy.bris.ac.uk
\t (00:00:05)
(00:00:06) Loading axlcore.cxt
\t (00:00:06) Opening existing design...
\d (00:00:06) Design opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_26.brd
\i (00:00:06) trapsize 2361
\i (00:00:06) trapsize 2429
\i (00:00:06) trapsize 2429
\i (00:00:07) trapsize 2237
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\i (00:00:10) zoom out 183.4060 -0.1901
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\i (00:00:11) roam start
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\i (00:00:11) roam y 144
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\i (00:00:11) roam y 32
\i (00:00:11) roam x -80
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\i (00:00:12) roam y -112
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\i (00:00:12) roam y -48
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\i (00:00:12) roam y 32
\i (00:00:13) roam end
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\i (00:00:13) zoom out 121.5373 40.1465
\i (00:00:13) trapsize 17900
\i (00:00:15) zoom in 1
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\i (00:00:15) zoom in 45.6419 17.8131
\i (00:00:15) trapsize 8950
\i (00:00:15) zoom in 1
\i (00:00:15) setwindow pcb
\i (00:00:15) zoom in 45.6420 17.8131
\i (00:00:15) trapsize 4475
\i (00:00:15) zoom in 1
\i (00:00:15) setwindow pcb
\i (00:00:15) zoom in 45.6420 17.8132
\i (00:00:15) trapsize 2237
\i (00:00:16) zoom out 1
\i (00:00:16) setwindow pcb
\i (00:00:16) zoom out 48.5060 18.3949
\i (00:00:16) trapsize 4475
\i (00:00:19) exit
\t (00:00:19) Journal end - Thu Feb 8 16:26:13 2018
\t (00:00:16) allegro 17.2 S028 Linux SPB 64-bit Edition
\t (00:00:16) Journal start - Fri May 4 11:01:04 2018
\t (00:00:16) Host=fortis.phy.bris.ac.uk User=phpgb Pid=8945 CPUs=4
\t (00:00:16) CmdLine= /software/CAD/Cadence/SPB172/tools/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_leds_pmt_pwr.cpm -product Allegro_performance -option Allegro_PCB_HighSpeed_Option -option Allegro_PCB_Mini_Option -mpssession phpgb_ProjectMgr14711 -mpshost fortis.phy.bris.ac.uk
\t (00:00:16)
(00:00:16) Loading axlcore.cxt
\t (00:00:17) Opening existing design...
\d (00:00:17) Design opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_26.brd
\i (00:00:17) trapsize 2590
\i (00:00:17) trapsize 2672
\i (00:00:17) trapsize 2672
\i (00:00:17) trapsize 2442
\i (00:00:18) etchedit
\i (00:00:25) zoom out 1
\i (00:00:25) setwindow pcb
\i (00:00:25) zoom out 192.0689 7.4889
\i (00:00:25) trapsize 4883
\i (00:00:25) zoom out 1
\i (00:00:25) setwindow pcb
\i (00:00:25) zoom out 192.0690 7.4889
\i (00:00:25) trapsize 9766
\i (00:00:26) zoom in 1
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\i (00:00:26) zoom in 191.2876 35.4204
\i (00:00:26) trapsize 4883
\i (00:00:27) zoom in 1
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\i (00:00:27) zoom in 1
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom in 202.1282 34.6391
\i (00:00:27) trapsize 1221
\i (00:00:59) xrefdes R4
\i (00:00:59) xrefdes R4
\i (00:00:59) xname_flush
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\i (00:01:17) trapsize 1254
\i (00:01:19) zoom out 1
\i (00:01:19) setwindow pcb
\i (00:01:19) zoom out 203.5702 32.4863
\i (00:01:19) trapsize 2508
\i (00:01:20) zoom in 1
\i (00:01:20) setwindow pcb
\i (00:01:20) zoom in 196.2483 34.9437
\i (00:01:20) trapsize 1254
\i (00:01:21) zoom in 1
\i (00:01:21) setwindow pcb
\i (00:01:21) zoom in 196.2484 34.9437
\i (00:01:21) trapsize 627
\i (00:01:22) zoom out 1
\i (00:01:22) setwindow pcb
\i (00:01:22) zoom out 196.6622 35.0315
\i (00:01:22) trapsize 1254
\i (00:01:24) pop dyn_option_select 'Application Mode@:@General Edit'
\i (00:01:24) generaledit
\i (00:01:34) pop dyn_option_select 'Application Mode@:@Placement Edit'
\i (00:01:34) placementedit
\i (00:01:37) setwindow form.find
\i (00:01:37) FORM find all_on
\i (00:01:40) setwindow pcb
\i (00:01:40) pop dyn_option_select 'Application Mode@:@General Edit'
\i (00:01:40) generaledit
\i (00:01:41) setwindow form.find
\i (00:01:41) FORM find all_on
\i (00:01:44) setwindow pcb
\i (00:01:44) drag_start grid 196.9881 34.8560
\i (00:01:44) move
\t (00:01:44) last pick: 196.5000 34.5000
\t (00:01:44) Pick new location for the element(s).
\i (00:01:46) drag_stop grid 194.4305 33.1258
\i (00:01:46) generaledit
\i (00:01:47) drag_start grid 195.5839 31.3204
\i (00:01:47) move
\t (00:01:47) last pick: 197.0000 31.5000
\t (00:01:47) Pick new location for the element(s).
\i (00:01:48) drag_stop grid 196.2108 34.6805
\i (00:01:49) generaledit
\i (00:01:49) drag_start grid 194.9320 33.2011
\i (00:01:49) move
\t (00:01:50) last pick: 194.5000 33.0000
\t (00:01:50) Pick new location for the element(s).
\i (00:01:53) drag_stop grid 195.5338 31.3957
\i (00:01:53) generaledit
\i (00:01:53) zoom out 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom out 192.9009 33.5521
\i (00:01:53) trapsize 2508
\i (00:01:55) zoom out 1
\i (00:01:55) setwindow pcb
\i (00:01:55) zoom out 192.8507 33.6524
\i (00:01:55) trapsize 5015
\i (00:01:57) save_as
\i (00:02:06) fillin "fmc_tlu_leds_pmt_pwr_27.brd"
\i (00:02:07) generaledit
\i (00:02:10) zoom in 1
\i (00:02:10) setwindow pcb
\i (00:02:10) zoom in 204.9871 35.0567
\i (00:02:10) trapsize 2508
\i (00:02:11) zoom in 1
\i (00:02:11) setwindow pcb
\i (00:02:11) zoom in 204.5859 34.8060
\i (00:02:11) trapsize 1254
\i (01:39:29) exit
\t (01:39:29) Journal end - Fri May 4 12:40:17 2018
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/batch_drc.log
View file @ 0de2161e
......@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : fmc_tlu_leds_pmt_pwr_25.brd )
( Drawing : fmc_tlu_leds_pmt_pwr_31.brd )
( Software Version : 17.2S028 )
( Date/Time : Tue Feb 6 12:58:49 2018 )
( Date/Time : Mon Jun 4 13:51:35 2018 )
( )
(---------------------------------------------------------------------)
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/comps_fmc_tlu_leds_pmt_pwr_31.out 0 → 100644
View file @ 0de2161e
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/crosssection_fmc_tlu_leds_pmt_pwr_31.out 0 → 100644
View file @ 0de2161e
Cross Section Report
/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_31.brd
Wed May 9 19:22:28 2018
Design Cross Section
Subclass Name,Type,Material,Thickness (MM),Tol +,Tol -,Conductivity (mho/cm),Dielectric Constant,Loss Tangent,Negative Artwork,Shield,Width (MM),Unused Pin Pad Suppression,Unused Via Pad Suppression
,SURFACE,AIR,,,,0,1,0,,,,,
TOP,CONDUCTOR,COPPER,0.03048,0,0,595900,4.5,0,,,0.1300,,
,DIELECTRIC,FR-4,0.2032,0,0,0,4.5,0.035,,,,,
L2,PLANE,COPPER,0.018,0,0,595900,4.5,0.035,,Yes,,,
,DIELECTRIC,FR-4,1.000000,0,0,0,4.5,0.035,,,,,
L3,PLANE,COPPER,0.018,0,0,595900,4.5,0.035,,Yes,,,
,DIELECTRIC,FR-4,0.2032,0,0,0,4.5,0.035,,,,,
BOTTOM,CONDUCTOR,COPPER,0.03048,0,0,595900,4.5,0,,,0.1300,,
,SURFACE,AIR,,,,0,1,0,,,,,
Total Thickness: 1.50336 MM
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/dbdoctor.log
View file @ 0de2161e
......@@ -2,9 +2,9 @@
( )
( DBDOCTOR )
( )
( Drawing : fmc_tlu_leds_pmt_pwr_24.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Wed Nov 15 12:08:55 2017 )
( Drawing : fmc_tlu_leds_pmt_pwr_31.brd )
( Software Version : 17.2S028 )
( Date/Time : Wed May 9 19:22:05 2018 )
( )
(---------------------------------------------------------------------)
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/films_fmc_tlu_leds_pmt_pwr_31.out 0 → 100644
View file @ 0de2161e
A!FILM_NAME!CLASS!SUBCLASS!ROTATION!OFFSET_X!OFFSET_Y!UNDEFINED_LINE_WIDTH!SHAPE_BOUNDING_BOX!PLOT_MODE!FILM_MIRRORED!FULL_CONTACT_THERMAL_RELIEFS!SUPPRESS_UNCONNECTED_PADS!DRAW_MISSING_PAD_APERTURES!USE_APERTURE_ROTATION!SUPPRESS_SHAPE_FILL!VECTOR_BASED_PAD_BEHAVIOR!
J!/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_31.brd!May 9 19:22:26 2018!355.0208!-64.9792!149.5560!-147.4440!4!millimeters!!!4!out of date!
S!L1!ETCH!TOP!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L1!PIN!TOP!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L1!VIA CLASS!TOP!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L2!ETCH!L2!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L2!PIN!L2!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L2!VIA CLASS!L2!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L3!ETCH!L3!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L3!PIN!L3!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L3!VIA CLASS!L3!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L4!ETCH!BOTTOM!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L4!PIN!BOTTOM!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!L4!VIA CLASS!BOTTOM!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!SP4!PACKAGE GEOMETRY!PASTEMASK_BOTTOM!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!SP4!PIN!PASTEMASK_BOTTOM!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!SP1!PACKAGE GEOMETRY!PASTEMASK_TOP!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!SP1!PIN!PASTEMASK_TOP!0!0.0000!0.0000!0.0000!2.5400!positive!no!no!no!no!no!no!yes!
S!SS4!BOARD GEOMETRY!SILKSCREEN_BOTTOM!0!0.0000!0.0000!0.2000!2.5400!positive!no!no!no!no!no!no!yes!
S!SS4!MANUFACTURING!AUTOSILK_BOTTOM!0!0.0000!0.0000!0.2000!2.5400!positive!no!no!no!no!no!no!yes!
S!SS1!PACKAGE GEOMETRY!SILKSCREEN_TOP!0!0.0000!0.0000!0.2000!2.5400!positive!no!no!no!no!no!no!yes!
S!SS1!MANUFACTURING!AUTOSILK_TOP!0!0.0000!0.0000!0.2000!2.5400!positive!no!no!no!no!no!no!yes!
S!SS1!BOARD GEOMETRY!SILKSCREEN_TOP!0!0.0000!0.0000!0.2000!2.5400!positive!no!no!no!no!no!no!yes!
S!SM4!BOARD GEOMETRY!SOLDERMASK_BOTTOM!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!SM4!PACKAGE GEOMETRY!SOLDERMASK_BOTTOM!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!SM4!PIN!SOLDERMASK_BOTTOM!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!SM1!BOARD GEOMETRY!SOLDERMASK_TOP!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!SM1!PACKAGE GEOMETRY!SOLDERMASK_TOP!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!SM1!PIN!SOLDERMASK_TOP!0!0.0000!0.0000!0.1270!2.5400!positive!no!no!no!no!no!no!yes!
S!OUTLINE!BOARD GEOMETRY!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!REF DES!ASSEMBLY_TOP!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!PACKAGE GEOMETRY!ASSEMBLY_TOP!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!DRAWING FORMAT!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!DRAWING FORMAT!TITLE_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!DRAWING FORMAT!TITLE_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!DRAWING FORMAT!REVISION_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!DRAWING FORMAT!REVISION_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!BOARD GEOMETRY!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!AST!BOARD GEOMETRY!DIMENSION!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!REF DES!ASSEMBLY_BOTTOM!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!PACKAGE GEOMETRY!ASSEMBLY_BOTTOM!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!DRAWING FORMAT!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!DRAWING FORMAT!TITLE_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!DRAWING FORMAT!TITLE_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!DRAWING FORMAT!REVISION_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!DRAWING FORMAT!REVISION_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!BOARD GEOMETRY!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!ASB!BOARD GEOMETRY!DIMENSION!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!MANUFACTURING!NCDRILL_LEGEND!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!MANUFACTURING!NCDRILL_FIGURE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!MANUFACTURING!XSECTION_CHART!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!MANUFACTURING!NCLEGEND-1-4!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!DRAWING FORMAT!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!DRAWING FORMAT!TITLE_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!DRAWING FORMAT!TITLE_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!DRAWING FORMAT!REVISION_BLOCK!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!DRAWING FORMAT!REVISION_DATA!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!BOARD GEOMETRY!OUTLINE!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
S!DD!BOARD GEOMETRY!DIMENSION!0!0.0000!0.0000!0.0500!2.5400!positive!no!no!no!no!no!no!yes!
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_22-1-4.drl → Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_31-1-4.drl
View file @ 0de2161e
M48
METRIC
T01C.5
T02C.8128
T03C.8999
T04C.9144
T05C1.
T06C1.1999
T07C1.7
T08C3.302
T01C.3302
T02C.5
T03C.8128
T04C.8999
T05C.9144
T06C1.
T07C1.1999
T08C1.7
T09C3.302
;LEADER: 12
;HEADER:
;CODE : ASCII
;FILE : fmc_tlu_leds_pmt_pwr_22-1-4.drl for ... layers TOP and BOTTOM
;DESIGN: fmc_tlu_leds_pmt_pwr_22.brd
;T01 Holesize 1. = 0.500000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 89
;T02 Holesize 2. = 0.812800 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T03 Holesize 3. = 0.899900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 32
;T04 Holesize 4. = 0.914400 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T05 Holesize 5. = 1.000000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 16
;T06 Holesize 6. = 1.199900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T07 Holesize 7. = 1.700000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T08 Holesize 8. = 3.302000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 6
;FILE : fmc_tlu_leds_pmt_pwr_31-1-4.drl for ... layers TOP and BOTTOM
;DESIGN: fmc_tlu_leds_pmt_pwr_31.brd
;T01 Holesize 1. = 0.330200 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T02 Holesize 2. = 0.500000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 107
;T03 Holesize 3. = 0.812800 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T04 Holesize 4. = 0.899900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 32
;T05 Holesize 5. = 0.914400 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T06 Holesize 6. = 1.000000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 16
;T07 Holesize 7. = 1.199900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T08 Holesize 8. = 1.700000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T09 Holesize 9. = 3.302000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 6
%
G90
T01
X07753000Y01805000
X08264000Y01825000
X07750000Y01746000
X08103000Y01825000
T02
X05697000Y00288000
X01991000Y03760000
X02009000Y02911000
X02218500Y02924500
X02580000Y03710000
X21380000Y03110000
X03514000Y03695000
......@@ -44,18 +51,28 @@ X21420000Y01520000
X21400000Y00800000
X19860000Y03200000
X19860000Y03500000
X15120000Y01730000
X11700000Y02656440
X03897000Y02755000
X04577000Y02755000
X06022000Y02527000
X07385000Y02137000
X08649000Y02726000
X10291000Y02295000
X15308000Y01598000
X11559510Y02394580
X11540000Y02696000
X15410000Y01460000
X11300000Y02460000
X11318000Y02571300
X11623000Y01560000
X08470000Y01010000
X13240000Y01670000
X08120000Y01180000
X08262000Y00649000
X16066000Y01172500
X05608000Y00891500
X10649000Y01604000
X08916000Y00876000
X08915000Y01300000
X08917000Y01550000
X10666000Y01441500
X05205000Y00745000
X04800000Y00600000
X03875540Y00795540
......@@ -81,6 +98,13 @@ X15374300Y01110000
X17333180Y00960000
X16336820Y00800000
X06636820Y00800000
X00941000Y02750000
X00942000Y02550000
X00945000Y02350000
X10181000Y01528000
X09648000Y01071000
X09758000Y01550000
X09846500Y00871000
X20500000Y01460000
X10100000Y02000000
X08560000Y02040000
......@@ -98,7 +122,6 @@ X03770000Y01000000
X04610000Y01581010
X01177490Y03710000
X01442500Y03847500
X02072500Y03847500
X21300000Y02150000
X21450000Y01200000
X20700000Y01250000
......@@ -113,7 +136,7 @@ X22690000Y03060000
X22690000Y01140000
X06963180Y00800000
X16663180Y00800000
T02
T03
X14000000Y00500000
X14000000Y01400000
X14000000Y01000000
......@@ -122,7 +145,7 @@ X08480000Y00600000
X11350000Y01030000
X05100000Y01900000
X04000000Y01320000
T03
T04
X10627000Y02794000
X10627000Y03048000
X10373000Y03048000
......@@ -155,7 +178,7 @@ X04919000Y02540000
X05681000Y02540000
X05681000Y03302000
X04919000Y03302000
T04
T05
X22300000Y02653000
X22300000Y00875000
X22300000Y01129000
......@@ -164,7 +187,7 @@ X23824000Y03161000
X23824000Y02653000
X23824000Y01129000
X23824000Y00875000
T05
T06
X13489000Y01327000
X11711000Y01327000
X13489000Y01073000
......@@ -181,13 +204,13 @@ X12981000Y01073000
X12981000Y01327000
X13235000Y01073000
X13235000Y01327000
T06
T07
X19000000Y01038000
X19254000Y01038000
T07
T08
X19000000Y00320000
X19254000Y00320000
T08
T09
X00400000Y00400000
X17570000Y03600000
X12455000Y03600000
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_OUTLINE.art
View file @ 0de2161e
G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_leds_pmt_pwr_24.brd*
G04 Layout Name: fmc_tlu_leds_pmt_pwr_31.brd*
G04 Film Name: fmc_tlu_leds_pmt_pwr_OUTLINE*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S079*
G04 Origin Date: Wed Nov 15 12:08:59 2017*
G04 File Origin: Cadence Allegro 17.2-S028*
G04 Origin Date: Wed May 9 19:22:06 2018*
G04 *
G04 Layer: BOARD GEOMETRY/OUTLINE*
G04 *
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_SM4.art
View file @ 0de2161e
G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: fmc_tlu_leds_pmt_pwr_24.brd*
G04 Layout Name: fmc_tlu_leds_pmt_pwr_31.brd*
G04 Film Name: fmc_tlu_leds_pmt_pwr_SM4*
G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-2015-S079*
G04 Origin Date: Wed Nov 15 12:08:58 2017*
G04 File Origin: Cadence Allegro 17.2-S028*
G04 Origin Date: Wed May 9 19:22:06 2018*
G04 *
G04 Layer: BOARD GEOMETRY/SOLDERMASK_BOTTOM*
G04 Layer: PACKAGE GEOMETRY/SOLDERMASK_BOTTOM*
......@@ -45,12 +45,14 @@ X1000000Y3575000D03*
Y3425000D03*
X1700000Y3575000D03*
Y3425000D03*
X3443000Y3421000D03*
Y3271000D03*
X3900000Y3375000D03*
Y3225000D03*
X4100000Y3525000D03*
Y3375000D03*
X3700000Y3575000D03*
Y3425000D03*
X3626000Y3436000D03*
Y3286000D03*
X3520000Y3118000D03*
Y2968000D03*
X4600000Y3475000D03*
Y3325000D03*
X4300000Y3525000D03*
......@@ -77,14 +79,12 @@ X9300000Y3525000D03*
Y3375000D03*
X9100000Y3475000D03*
Y3325000D03*
X9800000Y3475000D03*
Y3325000D03*
X11700000Y3525000D03*
Y3375000D03*
X11400000Y3475000D03*
Y3325000D03*
X11200000Y3475000D03*
Y3325000D03*
X9696000Y3479000D03*
Y3329000D03*
X11538000Y3392000D03*
Y3242000D03*
X11334000Y3229000D03*
Y3079000D03*
X13300000Y3596000D03*
Y3446000D03*
X13800000Y3475000D03*
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/layers_fmc_tlu_leds_pmt_pwr_31.out 0 → 100644
View file @ 0de2161e
A!LAYER_SORT!LAYER_SUBCLASS!LAYER_ARTWORK!LAYER_USE!LAYER_CONDUCTOR!LAYER_DIELECTRIC_CONSTANT!LAYER_ELECTRICAL_CONDUCTIVITY!LAYER_MATERIAL!LAYER_SHIELD_LAYER!LAYER_THERMAL_CONDUCTIVITY!LAYER_THICKNESS!LAYER_TYPE!LAYER_LOSS_TANGENT!
J!/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/fmc_tlu_leds_pmt_pwr_31.brd!Wed May 9 19:22:29 2018!-64.9792!-147.4440!355.0208!149.5560!0.0001!millimeters!FMC_TLU_LEDS_PMT_PWR!59.187402 mil!4!UP TO DATE!
S!000000!!!!NO!1.000000!0 mho/cm!AIR!NO!!0 mil!SURFACE!0!
S!000001!TOP!POSITIVE!!YES!4.500000!595900 mho/cm!COPPER!NO!!1.200000 mil!CONDUCTOR!0!
S!000002!!!!NO!4.500000!0 mho/cm!FR-4!!!8.000000 mil!DIELECTRIC!0.035!
S!000003!L2!POSITIVE!EMBEDDED_PLANE!YES!4.500000!595900 mho/cm!COPPER!YES!!0.708661 mil!PLANE!0.035!
S!000004!!!!NO!4.500000!0 mho/cm!FR-4!!!39.370079 mil!DIELECTRIC!0.035!
S!000005!L3!POSITIVE!EMBEDDED_PLANE!YES!4.500000!595900 mho/cm!COPPER!YES!!0.708661 mil!PLANE!0.035!
S!000006!!!!NO!4.500000!0 mho/cm!FR-4!!!8.000000 mil!DIELECTRIC!0.035!
S!000007!BOTTOM!POSITIVE!!YES!4.500000!595900 mho/cm!COPPER!NO!!1.200000 mil!CONDUCTOR!0!
S!000008!!!!NO!1.000000!0 mho/cm!AIR!NO!!0 mil!SURFACE!0!
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/master.tag
View file @ 0de2161e
fmc_tlu_leds_pmt_pwr_26.brd
fmc_tlu_leds_pmt_pwr_31.brd
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/molex_105313-1202.dra.outdra
View file @ 0de2161e
A!CLASS!SUBCLASS!RECORD_TAG!PAD_STACK_NAME!GRAPHIC_DATA_NAME!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!NO_SHAPE_CONNECT!
J!Z:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/molex_105313-1202.dra!Wed Nov 15 12:09:29 2017!-64.9792!-147.4440!355.0208!149.5560!0.0001!millimeters!!10.400000 mil!2!UP TO DATE!
J!/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/molex_105313-1202.dra!Wed May 9 19:22:33 2018!-64.9792!-147.4440!355.0208!149.5560!0.0001!millimeters!!10.400000 mil!2!UP TO DATE!
S!DRAWING FORMAT!DRAWING_ORIGIN!1 1!!CROSS!0.0000!0.0000!0.4000!0.4000!0!!!!!!!
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/regions_fmc_tlu_leds_pmt_pwr_31.out 0 → 100644
View file @ 0de2161e
A!CLASS!SUBCLASS!RECORD_TAG!GRAPHIC_DATA_NAME!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!REGION_NAME!
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/signoise.log
View file @ 0de2161e
INFO: Loaded existing device file 'Z:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_leds_pmt_pwr\physical\devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/devices.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file 'Z:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_leds_pmt_pwr\physical\devices.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file 'Z:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_leds_pmt_pwr\physical\devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/devices.dml'
INFO: Finished loading SigNoise device libraries
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