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AIDA-2020 TLU - Hardware
Commit 28520943 authored by David Cussans's avatar David Cussans
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Checking in files before requsting conversion of repository to Git

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Cadence/adw/shoppingCart.xml
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Cadence/copyproject.log
View file @ 28520943
INFO(COPYPROJ-87): Compiling a list of read-only files.
SUCCESS(COPYPROJ-88): Read-only files list compiled successfully.
INFO(COPYPROJ-81): Executing csnetlister -proj fmc_tlu_v1c.cpm.
INFO(COPYPROJ-81): Executing csnetlister -proj fmc_tlu_hdmi_rj45_lvds_adaptor_v2.cpm.
SUCCESS(COPYPROJ-83): Successfully executed csnetlister.
Source Info :
=============
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1c.cpm
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_hdmi_rj45_lvds_adaptor_v2.cpm
Library : fmc_tlu_v1_lib
Design : fmc_tlu_toplevel_c
Design : fmc_tlu_hdmi_rj45_lvds_adaptor_v2
Destination Info :
==================
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1e.cpm
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_hdmi_lemo_lvds_adaptor.cpm
Library : fmc_tlu_v1_lib
Design : fmc_tlu_toplevel_e
Design : fmc_tlu_hdmi_lemo_lvds_adaptor
INFO(COPYPROJ-17): Copying old design hierarchy.
SUCCESS(COPYPROJ-18): Copied old design hierarchy.
INFO(COPYPROJ-44): Updating variant view.
SUCCESS(COPYPROJ-45): Variants view updated successfully.
SUCCESS(COPYPROJ-48): Pxl state file in packaged view updated successfully.
INFO(COPYPROJ-64): Updating design data.
SUCCESS(COPYPROJ-65): Design data updated successfully.
SUCCESS(COPYPROJ-48): Pxl state file in packaged view updated successfully.
INFO(COPYPROJ-40): Updating opf view.
SUCCESS(COPYPROJ-41): Opf view updated successfully.
INFO(COPYPROJ-84): Executing nconcepthdl -proj "fmc_tlu_v1e.cpm" -scr "./cp_script.scr" -log "./cp_log.log" -ignoreprojscr.
SUCCESS(COPYPROJ-86): Successfully executed nconcepthdl.
INFO(COPYPROJ-84): Executing nconcepthdl -proj "fmc_tlu_hdmi_lemo_lvds_adaptor.cpm" -scr "./cp_script.scr" -log "./cp_log.log" -ignoreprojscr.
ERROR(COPYPROJ-85): Failure to execute nconcepthdl.
ERROR(COPYPROJ-85): Failure to execute nconcepthdl.
INFO(COPYPROJ-91): Starting to set back the read-only flag.
SUCCESS(COPYPROJ-92): Read-only flag set successfully for all files.
SUCCESS(COPYPROJ-67): Copy Project Success.
Cadence/cp_log.log
View file @ 28520943
Starting Non graphical Design Entry HDL (nconcepthdl)...
Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Allegro Design Entry HDL 17.2-2016 S028 (3666050) 10/1/2017
mpsdeclare
......@@ -17,7 +17,7 @@ set autoroute ON
set
set autoheavy ON
set
set attributes_dir "/eda/cadence/2016-17/RHELx86/SPB_16.60.079/tools/fet/concept/attributes"
set attributes_dir "/eda/cadence/2017-18/RHELx86/SPB_17.20.028/tools/fet/concept/attributes"
set
set dots_FILLED
set
......@@ -257,9 +257,9 @@ set hyperlinks on
set
set use_mono_as_symbol_color off
set
set preselect_flag ON
set preselect_flag off
set
set windowsmode_flag ON
set windowsmode_flag off
set
set delete_unattached_invisible_props ON
set
......@@ -385,6 +385,12 @@ set check_pack_sync_on_exit OFF
set
set check_pack_sync_on_import OFF
set
set allow_pinText_swap ON
set
set handle_prop_wrt_compangle OFF
set
set cds_dehdl_powertree OFF
set
set default_grid 0.0500 5
set
set default_body_grid 0.050 2
......@@ -392,10 +398,10 @@ set
set default_doc_grid 0.0500 5
set
INFO(SPCOCN-1737): Reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/cds.lib file.
nmapedit fmc_tlu_toplevel_e
nmapedit fmc_tlu_hdmi_lemo_lvds_adaptor
nmapedit
_!editincontext
INFO(SPCOCN-1446): New schematic FMC_TLU_TOPLEVEL_E.SCH.1.1 started as drawing #1.
INFO(SPCOCN-1446): New schematic FMC_TLU_HDMI_LEMO_LVDS_ADAPTOR.SCH.1.1 started as drawing #1.
library
library
library
......@@ -431,185 +437,25 @@ pptadd
pptadd
pptadd
get
INFO(SPCOCN-1445): Reading FMC_TLU_TOPLEVEL_E.SCH.1.1 into drawing #1.
INFO(SPCOCN-1445): Reading FMC_TLU_HDMI_LEMO_LVDS_ADAPTOR.SCH.1.1 into drawing #1.
hier_write
INFO(SPCOCN-1019): Save All completed.
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>PC023A_VTHRESH_BUFFER.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block pc023a_vthresh_buffer
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_DIODE_CLAMP_B.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_diode_clamp_b
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_HDMI_DUT_CONNECTOR.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_hdmi_dut_connector
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_THRESHOLD_DISCRIMINATOR_DUAL.SCH.1.1:
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_HDMI_LEMO_LVDS_ADAPTOR.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
CSDirect Allegro Design Entry HDL 17.2-2016 S028 (3666050) 10/1/2017
Netlisting block fmc_tlu_threshold_discriminator_dual
Netlisting block fmc_tlu_hdmi_lemo_lvds_adaptor
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_CLOCK_GEN.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_CLOCK_GEN.SCH.1.2:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1727): Appending master.tag page1.csa with page2.csa
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_clock_gen
Processing page 2
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_DAC_VTHRESH.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_dac_vthresh
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_VSUPPLY5V.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_vsupply5v
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>PC036A_FMC_LPC_CONNECTOR.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block pc036a_fmc_lpc_connector
Processing page 1
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_TOPLEVEL_E.SCH.1.1:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
WARNING(SPCOCN-1007): The following pages of this drawing must be written to create the parent-child dependency information: 2 3 4 5.
Use the UPREV_WRITE command to write all pages of the drawing.
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_TOPLEVEL_E.SCH.1.2:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1727): Appending master.tag page1.csa with page2.csa
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
WARNING(SPCOCN-1007): The following pages of this drawing must be written to create the parent-child dependency information: 3 4 5.
Use the UPREV_WRITE command to write all pages of the drawing.
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_TOPLEVEL_E.SCH.1.3:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1727): Appending master.tag page1.csa with page3.csa
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
WARNING(SPCOCN-1007): The following pages of this drawing must be written to create the parent-child dependency information: 4 5.
Use the UPREV_WRITE command to write all pages of the drawing.
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_TOPLEVEL_E.SCH.1.4:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1727): Appending master.tag page1.csa with page4.csa
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
WARNING(SPCOCN-1006): Page 5 of this drawing must be written to create the parent-child dependency information.
INFO(SPCOCN-1070): Checking drawing...
INFO(SPCOCN-1028): writing <fmc_tlu_v1_lib>FMC_TLU_TOPLEVEL_E.SCH.1.5:
INFO(SPCOCN-1044): writing binary file...
INFO(SPCOCN-1049): writing ASCII file...
INFO(SPCOCN-1727): Appending master.tag page1.csa with page5.csa
INFO(SPCOCN-1053): writing connectivity file...
INFO(SPCOCN-1054): ...written
CSDirect Allegro Design Entry HDL 16.6-S079 (v16-6-112GU) 10/4/2016
Netlisting block fmc_tlu_toplevel_e
Processing page 1
Processing page 3
Processing page 2
Processing page 4
Processing page 5
No netlisting errors found.
mapedit
_!editincontext
ERROR(SPCOCN-2122): Error(s)/ Warning(s) were found during save hierarchy while processing drawing(s)
fmc_tlu_clock_gen
You may load the marker files in dir temp/hierwrite to traverse errors.
INFO(SPCOCN-2121): Save hierarchy completed successfully.
exit
Cadence/fmc_tlu_leds_pmt_pwr.cpm
View file @ 28520943
{ Machine generated file created by SPI }
{ Last modified was 14:34:56 Wednesday, February 07, 2018 }
{ Last modified was 17:38:45 Wednesday, May 09, 2018 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -32,10 +32,10 @@ PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'C4' 'c12' 'r2' 'C9' 'C1'
AUTO_UPDATE_DEFAULT_MODELS 'ON'
PAPER_SIZE '9'
PAPER_SIZE '8'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME '\\its-zonedprint.cse.bris.ac.u'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
......@@ -67,8 +67,8 @@ show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_leds_pmt_pwr/bom/BOM_summary.csv'
last_template_file 'Z:/cad/tools/cadence_templates/spreadsheet-format.bom'
last_output_file './worklib/fmc_tlu_leds_pmt_pwr/bom/BOM_1per_line.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
......
Cadence/fmc_tlu_v1e.cpm
View file @ 28520943
{ Machine generated file created by SPI }
{ Last modified was 12:14:53 Friday, February 02, 2018 }
{ Last modified was 12:50:37 Friday, June 01, 2018 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -44,7 +44,7 @@ PAPER_SOURCE '15'
WPLOTTER_NAME 'PDF Writer - bioPDF'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
SEARCH_HISTORY 'I2C_RESET*' 'cn1_1' 'r1_6' 'd1_6' 'J1_9'
SEARCH_HISTORY 'TP6' 'I2C_RESET*' 'cn1_1' 'r1_6' 'd1_6'
END_CONCEPTHDL
START_PKGRXL
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/compview.dat,1 0 → 100755
View file @ 28520943
A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_02p_v16.brd!Thu Jul 07 13:57:26 2016!-35.0000!-75.0000!180.0000!225.0000!0.0001!millimeters!FMC_TLU_CLOCK_GEN!64.921260 mil!6!UP TO DATE!
S!IC1!73!!!DS92001!!DS92001TLD!!
S!IC2!62!!!DS92001!!DS92001TLD!!
S!IC3!72!!!DS92001!!DS92001TLD!!
S!IC4!61!!!DS92001!!DS92001TLD!!
S!IC5!60!!!DS92001!!DS92001TLD!!
S!IC7!28!!!DS92001!!DS92001TLD!!
S!C31!89!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C32!88!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C33!87!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C34!86!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C35!85!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C36!84!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!LK1!34!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK2!33!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK3!13!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK4!6!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!QZ1!42!!!OSC_6P_ENDIS_OUTP_OUTN!!BF-100.000MBE-T!!
S!C37!82!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C11!49!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C12!48!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C14!45!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C15!43!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C17!36!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C19!32!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C22!26!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C23!25!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C25!20!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C27!93!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C28!92!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C29!91!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C30!90!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C1!81!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C2!79!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C3!76!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C4!75!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C5!71!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C6!94!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C10!50!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C18!35!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C20!31!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C8!55!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C9!54!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C16!40!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C24!21!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C26!19!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C13!47!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C21!27!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C7!57!!!CAPCERSMDCL2!!CAPCERSMDCL2_1210-10UF,10V_GEN!!
S!CN1!69!!!CAPN4I!!CAPN4I-1UF,16V,X5R,GNM21!!
S!CN2!23!!!CAPN4I!!CAPN4I-1UF,16V,X5R,GNM21!!
S!L1!78!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L2!77!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L3!65!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L4!64!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L8!38!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!J1!30!!!CON3P!!CON3P-SIL254D!!
S!L5!53!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L6!52!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L7!51!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!U1!41!!!LP38692SD!!LP38692SD_WSON-1.8V,TEXAS INSTRUMENTS!!
S!LM1!56!!!PLEMO2CI!!PLEMO2CI-EPG.00.302.NLN!!
S!RN1!74!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!RN2!63!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!RN3!29!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!R26!83!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R1!68!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R2!67!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R3!59!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R4!58!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R9!24!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R10!22!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R12!17!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R19!9!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R24!2!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R25!1!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R5!46!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R11!18!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R13!16!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R14!15!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R15!14!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R16!12!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R17!11!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R18!10!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R20!8!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R21!7!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R22!5!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R23!4!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R6!44!!!RSMD0603!!RSMD0603_1/10W-4.7K,1%!!
S!R7!39!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!R8!37!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!IC8!3!!!SI5345!!SI5345A-B-GM!!
S!IC6!66!!!SN65MLVD040!!SN65MLVD040RGZ!!
S!D3!80!!!USBLC6-2!!USBLC6-2SC6!!
Cadence/worklib/fmc_tlu_clock_gen/packaged/dessync.log 0 → 100755
View file @ 28520943
Design Differences 16.6-S051 (v16-6-112ED) 6/8/2015
Cadence Design Systems, Inc.
(C) Copyright 1994, Cadence Design Systems, Inc.
Load design differences view at 11:47:21 Wednesday, March 29, 2017
--- Ignored Instance Property List ---
SCH_SIZE
HAS_FIXED_SIZE
DES
PRIM_FILE
CDS_LIB
DRAWING
PATH
XY
*************************************************************
* Loading logical design view of fmc_tlu_clock_gen(sch_1) *
*************************************************************
Setting design view directives...
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged\pstchip.dat
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged\pstxprt.dat
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged\pstxnet.dat
packaging the design view...
*****************************************************************
* End loading logical design view of fmc_tlu_clock_gen(sch_1) *
*****************************************************************
**********************************************************************************************
* Loading physical design view of fmc_tlu_clock_gen(fmc_tlu_clk_gen_02p_v21_allrouted.brd) *
**********************************************************************************************
Setting design view directives...
INFO(SPCODD-181): Loading P:/cad/bris_cdslib/lib_psd14.x/cds_analogue/cds_analogue.ptf.
INFO(SPCODD-181): Loading P:/cad/bris_cdslib/lib_psd14.x/cds_connectors/cds_connectors.ptf.
INFO(SPCODD-181): Loading P:/cad/bris_cdslib/lib_psd14.x/cds_logic/cds_logic.ptf.
INFO(SPCODD-181): Loading P:/cad/bris_cdslib/lib_psd14.x/cds_pld/cds_pld.ptf.
INFO(SPCODD-181): Loading P:/cad/bris_cdslib/lib_psd14.x/cds_special/cds_special.ptf.
INFO(SPCODD-181): Loading P:/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf.
INFO(SPCODD-181): Loading P:/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf.
INFO(SPCODD-181): Loading P:/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf.
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged/funcview.dat
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged/compview.dat
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged/netview.dat
Loading... P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_clock_gen\packaged/pinview.dat
packaging the design view...
**************************************************************************************************
* End loading physical design view of fmc_tlu_clock_gen(fmc_tlu_clk_gen_02p_v21_allrouted.brd) *
**************************************************************************************************
*******************************************
* Generating the design view difference *
*******************************************
***********************************************
* End generating the design view difference *
***********************************************
Writing project directives...
Exit Design Differences
Cadence/worklib/fmc_tlu_clock_gen/packaged/funcview.dat,1 0 → 100755
View file @ 28520943
This diff is collapsed.
Cadence/worklib/fmc_tlu_clock_gen/packaged/netview.dat,1 0 → 100755
View file @ 28520943
A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_02p_v16.brd!Thu Jul 07 13:57:27 2016 CONSTRAINTS_VIEW_GENERATED!-35.0000!
S!ENABLE_DUT_CLK_FROM_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(1)!!
S!XA!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):xa!!
S!XB!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):xb!!
S!VDDO_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vddo_clk40!!
S!UNNAMED_3_RSMD0603_I87_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i87_b!!
S!UNNAMED_3_RSMD0603_I87_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i87_a!!
S!UNNAMED_3_RSMD0603_I86_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i86_b!!
S!UNNAMED_3_RSMD0603_I86_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i86_a!!
S!UNNAMED_3_RSMD0603_I69_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i69_b!!
S!UNNAMED_3_RSMD0603_I68_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i68_b!!
S!UNNAMED_3_RSMD0603_I65_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i65_b!!
S!UNNAMED_3_RSMD0603_I64_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i64_b!!
S!UNNAMED_3_RSMD0603_I62_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i62_b!!
S!UNNAMED_3_RSMD0603_I60_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i60_b!!
S!UNNAMED_3_RSMD0603_I58_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i58_b!!
S!UNNAMED_3_RSMD0603_I57_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i57_b!!
S!UNNAMED_3_PLEMO2CI_I7_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_plemo2ci_i7_b!!
S!UNNAMED_3_PLEMO2CI_I7_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_plemo2ci_i7_a!!
S!UNNAMED_3_OSC6PENDISOUTPOUTN_I3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_osc6pendisoutpoutn_i37_endis!!
S!UNNAMED_3_LP38692SD_I85_EN!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_lp38692sd_i85_en!!
S!UNNAMED_3_CAPN4I_I11_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capn4i_i11_a!!
S!UNNAMED_3_CAPCERSMDCL2_I45_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i45_b!!
S!UNNAMED_3_CAPCERSMDCL2_I44_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i44_b!!
S!UNNAMED_3_1-HOLE_I95_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\unnamed_3_1-hole_i95_a\!!
S!UNNAMED_3_1-HOLE_I94_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\unnamed_3_1-hole_i94_a\!!
S!UNNAMED_1_COMMONMODELINEFILTE_7!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i228_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_6!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i228_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_5!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i210_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_4!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i210_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i194_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_2!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i194_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_1!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i80_2!!
S!UNNAMED_1_COMMONMODELINEFILTER_!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i80_1!!
S!UNNAMED_1_CAPN4I_I83_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i83_a!!
S!UNNAMED_1_CAPN4I_I224_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i224_a!!
S!UNNAMED_1_CAPN4I_I205_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i205_a!!
S!UNNAMED_1_CAPN4I_I190_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i190_a!!
S!SDA!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):sda!!
S!SCL!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):scl!!
S!RST*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\rst*\!!
S!LOL*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\lol*\!!
S!LEMO_CLK_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):lemo_clk_p!!
S!LEMO_CLK_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):lemo_clk_n!!
S!INTR*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\intr*\!!
S!ENABLE_DUT_CLK_FROM_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(3)!!
S!ENABLE_DUT_CLK_FROM_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(2)!!
S!ENABLE_CLK_TO_DUT<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(2)!!
S!ENABLE_DUT_CLK_FROM_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(0)!!
S!ENABLE_CLK_TO_LEMO!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_lemo!!
S!ENABLE_CLK_TO_DUT<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(1)!!
S!ENABLE_CLK_TO_DUT<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(3)!!
S!ENABLE_CLK_TO_DUT<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(0)!!
S!DUT_CLK_TO_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(3)!!
S!DUT_CLK_TO_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(2)!!
S!DUT_CLK_TO_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(1)!!
S!DUT_CLK_TO_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(0)!!
S!DUT_CLK_FROM_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(3)!!
S!DUT_CLK_FROM_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(2)!!
S!DUT_CLK_FROM_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(1)!!
S!DUT_CLK_FROM_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(0)!!
S!CLK_TO_LEMO_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_lemo_p!!
S!CLK_TO_LEMO_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_lemo_n!!
S!CLK_TO_FPGA_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_fpga_p!!
S!CLK_TO_FPGA_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_fpga_n!!
S!CLK_TO_DUT_P<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(3)!!
S!CLK_TO_DUT_P<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(2)!!
S!CLK_TO_DUT_P<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(1)!!
S!CLK_TO_DUT_P<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(0)!!
S!CLK_TO_DUT_N<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(3)!!
S!CLK_TO_DUT_N<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(2)!!
S!CLK_TO_DUT_N<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(1)!!
S!CLK_TO_DUT_N<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(0)!!
S!CLK_N<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(3)!!
S!CLK_N<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(2)!!
S!CLK_N<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(1)!!
S!CLK_N<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(0)!!
S!CLK_P<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(3)!!
S!CLK_P<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(2)!!
S!CLK_P<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(1)!!
S!CLK_P<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(0)!!
S!CLK_IO_2!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_2!!
S!CLK_IO_1_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_1_p!!
S!CLK_IO_1_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_1_n!!
S!CLK_FROM_LEMO_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_lemo_p!!
S!CLK_FROM_LEMO_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_lemo_n!!
S!CLK_FROM_HDMI_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_hdmi_p!!
S!CLK_FROM_HDMI_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_hdmi_n!!
S!CLK_FROM_FPGA_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_fpga_p!!
S!CLK_FROM_FPGA_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_fpga_n!!
S!VDD_OSC!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdd_osc!!
S!VDDA_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdda_clk40!!
S!VDD_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdd_clk40!!
S!P3V3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):p3v3!!
S!GND_SIGNAL!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):gnd_signal!!
Cadence/worklib/fmc_tlu_clock_gen/packaged/pinview.dat,1 0 → 100755
View file @ 28520943
This diff is collapsed.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstcmdb.dat,p 0 → 100755
View file @ 28520943
This diff is collapsed.
Cadence/worklib/fmc_tlu_hdmi__rj45_lvds_adaptor/sch_1/fmc_tlu_hdmi__rj45_lvds_adaptor.dcf,1
View file @ 28520943
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 3 )
( logicalViewRevNum 4 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -708,6 +708,12 @@
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i154_a\"
( objectStatus "unnamed_1_1-hole_i154_a" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i155_a\"
( objectStatus "unnamed_1_1-hole_i155_a" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i156_a\"
( objectStatus "unnamed_1_1-hole_i156_a" )
)
( gate "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):page1_i2"
( attribute "CDS_LIB" "bris_cds_connectors"
( Origin gPackager )
......@@ -4331,6 +4337,76 @@
( pin "a(0)"
)
)
( gate "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):page1_i155"
( attribute "CDS_LIB" "bris_cds_connectors"
( Origin gPackager )
)
( attribute "NO_LIST" "TRUE"
( Origin gFrontEnd )
)
( attribute "PACK_TYPE" "0-8"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "3"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(-700,-225)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "1-HOLE"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "1-HOLE_0-8-BASE"
( Origin gPackager )
)
( objectStatus "PAGE1_I155" )
( pin "a(0)"
)
)
( gate "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):page1_i156"
( attribute "CDS_LIB" "bris_cds_connectors"
( Origin gPackager )
)
( attribute "NO_LIST" "TRUE"
( Origin gFrontEnd )
)
( attribute "PACK_TYPE" "0-8"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "3"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(-350,-225)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "1-HOLE"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "1-HOLE_0-8-BASE"
( Origin gPackager )
)
( objectStatus "PAGE1_I156" )
( pin "a(0)"
)
)
)
)
)
Cadence/worklib/fmc_tlu_hdmi__rj45_lvds_adaptor/sch_1/fmc_tlu_hdmi__rj45_lvds_adaptor.dcf,2
View file @ 28520943
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 4 )
( logicalViewRevNum 5 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -690,29 +690,29 @@
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):unnamed_1_rsmd0603_i97_a"
( objectStatus "unnamed_1_rsmd0603_i97_a" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i149_a\"
( objectStatus "unnamed_1_1-hole_i149_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):hbusy"
( objectStatus "hbusy" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i150_a\"
( objectStatus "unnamed_1_1-hole_i150_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\hbusy*\"
( objectStatus "hbusy*" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i151_a\"
( objectStatus "unnamed_1_1-hole_i151_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):hclk"
( objectStatus "hclk" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i152_a\"
( objectStatus "unnamed_1_1-hole_i152_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\hclk*\"
( objectStatus "hclk*" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i153_a\"
( objectStatus "unnamed_1_1-hole_i153_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):hcont"
( objectStatus "hcont" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i154_a\"
( objectStatus "unnamed_1_1-hole_i154_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\hcont*\"
( objectStatus "hcont*" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i155_a\"
( objectStatus "unnamed_1_1-hole_i155_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):htrig"
( objectStatus "htrig" )
)
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\unnamed_1_1-hole_i156_a\"
( objectStatus "unnamed_1_1-hole_i156_a" )
( signal "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):\htrig*\"
( objectStatus "htrig*" )
)
( gate "@fmc_tlu_v1_lib.\fmc_tlu_hdmi__rj45_lvds_adaptor\(sch_1):page1_i2"
( attribute "CDS_LIB" "bris_cds_connectors"
......
Cadence/worklib/fmc_tlu_hdmi__rj45_lvds_adaptor/sch_1/fmc_tlu_hdmi__rj45_lvds_adaptor.dcf,3
View file @ 28520943
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 5 )
( logicalViewRevNum 6 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -3780,7 +3780,7 @@
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(4000,425)"
( attribute "XY" "(-1150,-825)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CON8P"
......@@ -3899,7 +3899,7 @@
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(4000,50)"
( attribute "XY" "(-425,-1375)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "RSMD0603"
......@@ -3988,7 +3988,7 @@
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(4000,-150)"
( attribute "XY" "(-425,-1575)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "RSMD0603"
......@@ -4047,7 +4047,7 @@
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(3700,50)"
( attribute "XY" "(-725,-1375)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
......@@ -4106,7 +4106,7 @@
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(3700,-150)"
( attribute "XY" "(-725,-1575)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/bom/BOM_summary.csv
View file @ 28520943
,,,,,,,,
TITLE, Bill of Materials,,,,,,,
DATE, 11/15/2017,,,,,,,
DESIGN, fmc_tlu_leds_pmt_pwr,,,,,,,
TEMPLATE, /projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom,,,,,,,
CALLOUT, bom.callouts,,,,,,,
,,,,,,,,
TITLE: Bill of Materials
DATE: 05/09/2018
DESIGN: fmc_tlu_leds_pmt_pwr
TEMPLATE: /projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom
CALLOUT: bom.callouts
Part Name,Ref Des,Qty,PART_NUMBER,PART_DESCRIPTION,OL_COMMENTS,KL_COMMENTS,PL_COMMENTS,Do Not Fit
24AA025E48T-I/SN,IC5,1,24AA025E48T-I/SN,?,?,?,?,?
AD5665RBRUZ-1,IC1,1,AD5665RBRUZ-1,?,?,?,?,?
"CAPCERSMDCL2_0603-100NF,16V","C5,C6,C70",3,CC0603_100NF_16V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-1UF,16V","C1,C3,C7,C8",4,CC0603_1UF_16V_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_1206-10UF,50V",C2,1,CC1206_10UF_50V_10%_X7R,?,?,?,?,?
"ELCAPTAN_SMD-2.2UF,20V",C4,1,B45196E4225M209,?,?,?,?,?
"CAPCERSMDCL2_0603-100NF,16V","C5,C6",2,CC0603_100NF_16V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0805-1UF,25V","C9,C10,C11,C12",4,GRM21BR71E105KA99,?,?,?,?,?
"CAPCERSMDCL2_1206-10UF,50V",C2,1,CC1206_10UF_50V_10%_X7R,?,?,?,?,?
CON16P-MTLW-108-07-L-D-250,J2,1,MTLW-108-07-L-D-250,?,?,?,?,?
DCDC_TRACO_TEN 3-1211,PW1,1,TEN 3-1211,?,?,?,?,?
DIODE_SCHOTTKY_CA-MBR130T1G,D1,1,MBR130T1G,?,?,?,?,?
"ELCAPTAN_SMD-2.2UF,20V",C4,1,B45196E4225M209,?,?,?,?,?
"FUSE-RESET-MINISMDC050,0.50A",F1,1,MINISMDC050F,?,?,?,?,?
AD5665RBRUZ-1,IC1,1,AD5665RBRUZ-1,?,?,?,?,?
PCA9539PW,"IC2,IC3",2,PCA9539PW,?,?,?,?,?
SK_RA_MOLEX_105313_1202-RA,J1,1,105313-1202,?,?,?,?,?
CON16P-MTLW-108-07-L-D-250,J2,1,MTLW-108-07-L-D-250,?,?,?,?,?
INDUCTANCE_SIMID1812T-1UH_10%,"L1,L2",2,B82432T1102K,?,?,?,?,?
HSMF-C113,"LD1,LD2,LD3,LD4,LD5,LD6,LD7,LD8,LD9,LD10,LD11,LD12,LD13,LD15",14,HSMF-C113,?,?,?,?,?
INDUCTANCE_SIMID1812T-1UH_10%,"L1,L2",2,B82432T1102K,?,?,?,?,?
LINK-0603-OPEN,"LO1,LO2,LO3",3,?,?,?,?,?,TRUE
LM1117-DTX-3.3,REG1,1,LM1117DTX-3.3,?,?,?,?,?
"LP5951_SOT23-5-1.3V,TEXAS INSTRUMENTS",U1,1,LP5951MF-1.3,"1.3V, 150mA Low Dropout Regulator",Farnell 1312651,-,-,?
PCA9539PW,"IC2,IC3",2,PCA9539PW,?,?,?,?,?
PLEMO4CI-EPL.0S.304.HLN,"LM1,LM2,LM3,LM4",4,EPL.0S.304.HLN,?,?,?,?,?
LINK-0603-OPEN,LO1,1,?,?,?,?,?,TRUE
DCDC_TRACO_TEN 3-1211,PW1,1,TEN 3-1211,?,?,?,?,?
"RSMD0603_1/10W-1K,1%","R1,R9,R10,R11,R12",5,R0603_1K_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_-00,","R2,R3,R4,R16,R17,R38,R39,R50,R55,R60,R62,R64",12,R0603_00_JUMPER,?,?,?,?,?
"RSMD0603_1/10W-1.6K,1%","R5,R6,R7,R8",4,R0603_1K6_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-180,1%","R13,R18,R21,R24,R27,R30,R33,R37,R42,R45",10,R0603_180R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-1K,1%",R1,1,R0603_1K_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-270,1%","R14,R15,R19,R20,R22,R23,R25,R26,R28,R29,R31,R32,R34,R35,R36,R40,R41,R43,R44,R46,R47,R48,R49,R51,R52",25,R0603_270R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_-00,","R2,R3,R4,R16,R17,R38,R39",7,R0603_00_JUMPER,?,?,?,?,?
"RSMD0603_1/10W-1.6K,1%","R5,R6,R7,R8",4,R0603_1K6_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-4.7K,1%","R53,R54",2,R0603_4K7_1%_0.1W_100PPM,?,?,?,?,?
LM1117-DTX-3.3,REG1,1,LM1117DTX-3.3,?,?,?,?,?
"RSMD0603_1/10W-5.6K,1%","R9,R10,R11,R12",4,R0603_5K6_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-XX,1%","R61,R63,R65",3,R0603_XX_1%_0.1W_100PPM,?,?,?,?,?
SK_RA_MOLEX_105313_1202-RA,J1,1,105313-1202,?,?,?,?,?
TP_HOLE-0.8MM,"TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8",8,TP_HOLE_0.8mm,?,?,?,?,?
"LP5951_SOT23-5-1.3V,TEXAS INSTRUMENTS",U1,1,LP5951MF-1.3,"1.3V, 150mA Low Dropout Regulator",Farnell 1312651,-,-,?
ZENER_SOD123-CA-BZT52-C13,ZD1,1,BZT52-C13,?,?,?,?,?
TOTAL, ,105, , , , , ,
TOTAL, ,117, , , , , ,
Cadence/worklib/fmc_tlu_leds_pmt_pwr/bom/bom.log
View file @ 28520943
Cadence Design Systems, Inc.
Bomhdl 16.6-S069 (v16-6-112FY) 4/20/2016
Bomhdl 17.2-2016 S028 (3666050) 10/1/2017
Copyright 2011 Cadence Design Systems, Inc, Cadence Design Systems, Inc.
Run on Wed Nov 15 12:10:38 2017
Run on Wed May 9 17:37:25 2018
*****************************
......@@ -42,7 +42,6 @@
Initializing tool communication modules...
Checking the presence of variant and BOM view.
Set the DDBPI message handlers and Tool start time.
Initialize jlg string table.
......@@ -108,6 +107,8 @@ INFO(SPCODD-181): Loading /projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd1
INFO(SPCODD-181): Loading /projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/cninterface/pca9539/part_table/pca9539.ptf.
INFO(SPCODD-181): Loading /projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/cnmemory/24aa025e48/part_table/24aa025e48.ptf.
INFO(SPCODD-181): Loading /projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/concept_libs/pe16/pe_cern_lib/cnconnector/con16p/part_table/con16p.ptf.
Design loaded successfully.
......@@ -143,5 +144,13 @@ Output file list :
*********************************
* End generating bom reports *
*********************************
Start time 17:37:25
End time 17:38:45
Elapsed time 0:01:20
*********************************
* BOM-HDL execution done. *
*********************************
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstback.dat
View file @ 28520943
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
{ Packager-XL run on 09-May-2018 AT 13:00:02 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_leds_pmt_pwr(sch_1):page1";
BODY = "CAPCERSMDCL2","I50": LOCATION = "C7" #&CDS_LOCATION = "C7" &SEC = "1" #&CDS_SEC = "1";
......@@ -155,6 +155,15 @@ BODY = "FUSE-RESET","I152": LOCATION = "F1" #&CDS_LOCATION = "F1" &SEC = "1" #&C
BODY = "SK_RA_MOLEX_105313_1202","I154": LOCATION = "J1" #&CDS_LOCATION = "J1" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"A<1>": PN = "2" !CDS_PN = "2";
BODY = "LINK-0603-OPEN","I157": LOCATION = "LO3" #&CDS_LOCATION = "LO3" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "LINK-0603-OPEN","I158": LOCATION = "LO2" #&CDS_LOCATION = "LO2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I159": LOCATION = "R55" #&CDS_LOCATION = "R55" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_leds_pmt_pwr(sch_1):page2";
BODY = "PCA9539","I1": LOCATION = "IC2" #&CDS_LOCATION = "IC2" &SEC = "1" #&CDS_SEC = "1";
"A0": PN = "21" !CDS_PN = "21";
......@@ -384,6 +393,35 @@ BODY = "RSMD0603","I201": LOCATION = "R51" #&CDS_LOCATION = "R51" &SEC = "1" #&C
BODY = "RSMD0603","I204": LOCATION = "R50" #&CDS_LOCATION = "R50" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I206": #LOCATION = "R64" !CDS_LOCATION = "R64" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I207": #LOCATION = "R62" !CDS_LOCATION = "R62" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "24AA025E48","I209": LOCATION = "IC5" #&CDS_LOCATION = "IC5" &SEC = "1" #&CDS_SEC = "1";
"A0": PN = "1" !CDS_PN = "1";
"A1": PN = "2" !CDS_PN = "2";
"A2": PN = "3" !CDS_PN = "3";
"SCL": PN = "6" !CDS_PN = "6";
"SDA": PN = "5" !CDS_PN = "5";
"VCC": PN = "8" !CDS_PN = "8";
"VSS": PN = "4" !CDS_PN = "4";
BODY = "CAPCERSMDCL2","I210": #LOCATION = "C70" !CDS_LOCATION = "C70" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I212": #LOCATION = "R65" !CDS_LOCATION = "R65" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I213": #LOCATION = "R63" !CDS_LOCATION = "R63" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I214": #LOCATION = "R60" !CDS_LOCATION = "R60" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I216": #LOCATION = "R61" !CDS_LOCATION = "R61" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_leds_pmt_pwr(sch_1):page3";
BODY = "CON16P","I146": LOCATION = "J2" #&CDS_LOCATION = "J2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstchip.dat
View file @ 28520943
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
{ Packager-XL run on 09-May-2018 AT 13:00:02 }
primitive '24AA025E48T-I/SN';
pin
'VCC':
PIN_NUMBER='(8)';
PINUSE='POWER';
NO_LOAD_CHECK='Both';
NO_IO_CHECK='Both';
NO_ASSERT_CHECK='TRUE';
NO_DIR_CHECK='TRUE';
ALLOW_CONNECT='TRUE';
'VSS':
PIN_NUMBER='(4)';
PINUSE='GROUND';
NO_LOAD_CHECK='Both';
NO_IO_CHECK='Both';
NO_ASSERT_CHECK='TRUE';
NO_DIR_CHECK='TRUE';
ALLOW_CONNECT='TRUE';
'SDA':
PIN_NUMBER='(5)';
BIDIRECTIONAL='TRUE';
INPUT_LOAD='(-0.01,0.01)';
OUTPUT_LOAD='(1.0,-1.0)';
PINUSE='BI';
'SCL':
PIN_NUMBER='(6)';
INPUT_LOAD='(-0.01,0.01)';
PINUSE='IN';
'A0':
PIN_NUMBER='(1)';
INPUT_LOAD='(-0.01,0.01)';
PINUSE='IN';
'A1':
PIN_NUMBER='(2)';
INPUT_LOAD='(-0.01,0.01)';
PINUSE='IN';
'A2':
PIN_NUMBER='(3)';
INPUT_LOAD='(-0.01,0.01)';
PINUSE='IN';
end_pin;
body
PART_NAME='24AA025E48';
BODY_NAME='24AA025E48';
PHYS_DES_PREFIX='IC';
CLASS='IC';
NC_PINS='(7)';
STATUS='Preferred';
PART_NUMBER='24AA025E48T-I/SN';
MANUFACTURER='MICROCHIP';
DESCRIPTION='2K I2C Serial EEPROM with EUI-48 Node Identity';
DATASHEET_URL='file://cern.ch/dfs/Services/cdslib/datasheets/24aa02e48.pdf~
';
PINCOUNT='8';
SMD='YES';
CASE='SOIC8';
JEDEC_TYPE='SOIC127P600X175-8N';
PARENT_PART_TYPE='24AA025E48_SOIC';
PARENT_PPT='24AA025E48';
PARENT_PPT_PART='24AA025E48T-I/SN';
end_body;
end_primitive;
primitive 'AD5665RBRUZ-1-GND=GND_SIGNAL,VA';
pin
'LDAC*':
......@@ -1205,6 +1267,46 @@ primitive 'RSMD0603_1/10W-5.6K,1%';
PARENT_PPT_PART='RSMD0603_1/10W-5.6K,1%';
end_body;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';
pin
'A'<0>:
PIN_NUMBER='(1)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
'B'<0>:
PIN_NUMBER='(2)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
end_pin;
body
PART_NAME='RSMD0603';
BODY_NAME='RSMD0603';
CLASS='DISCRETE';
PINCOUNT='2';
SIZE='1';
PHYS_DES_PREFIX='R';
DESCRIPTION='SMD Resistor';
CASE='0603';
SMD='YES';
STATUS='Not Preferred';
PART_NUMBER='R0603_XX_1%_0.1W_100PPM';
VALUE='XX';
TOL='1%';
PWR='0.1W';
JEDEC_TYPE='C0603';
MANUFACTURER='GENERIC';
MOUNTED='NO';
PARENT_PART_TYPE='RSMD0603_1/10W';
PARENT_PPT='RSMD0603';
PARENT_PPT_PART='RSMD0603_1/10W-XX,1%';
end_body;
end_primitive;
primitive 'SK_RA_MOLEX_105313_1202-RA';
pin
'A'<1>:
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstpin.dat
View file @ 28520943
FILE_TYPE=PINLIST;
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
TIME=' COMPILATION ON 07-Feb-2018 AT 14:34:47';
{ Packager-XL run on 09-May-2018 AT 13:00:02 }
TIME=' COMPILATION ON 09-May-2018 AT 13:00:02';
primitive '24AA025E48T-I/SN';body '24AA025E48';
'VCC':'(8)';
'VSS':'(4)';
'SDA':'(5)';BIDI;
'SCL':'(6)';IN;
'A0':'(1)';IN;
'A1':'(2)';IN;
'A2':'(3)';IN;
end_primitive;
primitive 'AD5665RBRUZ-1-GND=GND_SIGNAL,VA';body 'AD5665R';
'LDAC*':'(1)';IN;
'ADDR1':'(2)';IN;
......@@ -152,6 +161,10 @@ primitive 'RSMD0603_1/10W-5.6K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SK_RA_MOLEX_105313_1202-RA';body 'SK_RA_MOLEX_105313_1202';
'A'<1>:'(2)';
'A'<0>:'(1)';
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstrprt.dat
View file @ 28520943
......@@ -3,8 +3,9 @@
- PART SUMMARY -
24AA025E48T-I/SN 24AA025E48T-I/SN 1
AD5665RBRUZ-1-GND=GND_SIGNAL,VA AD5665RBRUZ-1 1
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 2
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 3
CAPCERSMDCL2_0603-1UF,16V CC0603_1UF_16V_10%_X5R 4
CAPCERSMDCL2_0805-1UF,25V GRM21BR71E105KA99 4
CAPCERSMDCL2_1206-10UF,50V CC1206_10UF_50V_10%_X7R 1
......@@ -15,20 +16,21 @@ ELCAPTAN_SMD-2.2UF,20V B45196E4225M209 1
FUSE-RESET-MINISMDC050,0.50A MINISMDC050F 1
HSMF-C113 HSMF-C113 14
INDUCTANCE_SIMID1812T-1UH_10% B82432T1102K 2
LINK-0603-OPEN 1
LINK-0603-OPEN 3
LM1117-DTX-3.3 LM1117DTX-3.3 1
LP5951_SOT23-5-1.3V,TEXAS INSTA LP5951MF-1.3 1
PCA9539PW-VDD=P3V3,VSS=GND_SIGA PCA9539PW 2
PLEMO4CI-EPL.0S.304.HLN-GND=GNA EPL.0S.304.HLN 4
RSMD0603_-00, R0603_00_JUMPER 8
RSMD0603_-00, R0603_00_JUMPER 12
RSMD0603_1/10W-1.6K,1% R0603_1K6_1%_0.1W_100PPM 4
RSMD0603_1/10W-180,1% R0603_180R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 1
RSMD0603_1/10W-270,1% R0603_270R_1%_0.1W_100PPM 25
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 2
RSMD0603_1/10W-5.6K,1% R0603_5K6_1%_0.1W_100PPM 4
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 3
SK_RA_MOLEX_105313_1202-RA 105313-1202 1
TP_HOLE-0.8MM TP_HOLE_0.8mm 8
ZENER_SOD123-CA-BZT52-C13 BZT52-C13 1
Total 106
Total 117
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pxl.chg
View file @ 28520943
{ Packager-XL run on 07-Feb-2018 AT 14:34:48.00 }
{ Packager-XL run on 09-May-2018 AT 13:00:03.00 }
BINDING CHANGES LIST
......@@ -7,6 +7,9 @@ DELETED BINDINGS:
CHANGED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I157@CDS_SPECIAL.LINK-0603-OPEN(CHIPS) LINK-0603-OPEN (0) IS ASSIGNED TO LO3 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I158@CDS_SPECIAL.LINK-0603-OPEN(CHIPS) LINK-0603-OPEN (0) IS ASSIGNED TO LO2 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I159@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_-00, (0) IS ASSIGNED TO R55 SECTION 1
END BINDING CHANGES LIST
......@@ -18,6 +21,9 @@ LOGICAL PARTS DELETED FROM DESIGN:
LOGICAL PARTS ADDED TO DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I157@CDS_SPECIAL.LINK-0603-OPEN(CHIPS) LINK-0603-OPEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I158@CDS_SPECIAL.LINK-0603-OPEN(CHIPS) LINK-0603-OPEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I159@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_-00, (0)
END LOGICAL CHANGES LIST
......@@ -26,6 +32,9 @@ PHYSICAL CHANGES LIST
PHYSICAL PARTS ADDED TO DESIGN:
LO3 LINK-0603-OPEN
LO2 LINK-0603-OPEN
R55 RSMD0603_-00,
PHYSICAL PARTS DELETED FROM DESIGN:
......@@ -40,5 +49,9 @@ LOGICAL NET DELETIONS:
LOGICAL NET ADDITIONS:
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):UNNAMED_1_LEDTRICOLOR4P1A3C_I138_C1' 'UNNAMED_1_LEDTRICOLOR4P1A3C_I_1' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):UNNAMED_1_LEDTRICOLOR4P1A3C_I138_C2' 'UNNAMED_1_LEDTRICOLOR4P1A3C_I_2' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):UNNAMED_1_LEDTRICOLOR4P1A3C_I138_C3' 'UNNAMED_1_LEDTRICOLOR4P1A3C_I_3' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):UNNAMED_2_LEDTRICOLOR4P1A3C_I64_C1' 'UNNAMED_2_LEDTRICOLOR4P1A3C__24' {ADDED}
END NET CHANGES LIST
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pxl.dbg
View file @ 28520943
Log File: C:\Users\phpgb\AppData\Local\Temp\s9fo.
Markers File: C:\Users\phpgb\AppData\Local\Temp\s9fo.1
Debug File: C:\Users\phpgb\AppData\Local\Temp\s9fo.3
Log File: /tmp/fileolitU4
Markers File: /tmp/fileIZW1Qu
Debug File: /tmp/fileMtSDOk
Debug[0] := TRUE
Elapsed time since start = (00:00:00)
......@@ -43,3 +43,5 @@ Elapsed time since start = (00:00:01)
DDB_INFO: State file for design FMC_TLU_LEDS_PMT_PWR successfully written.
DDB_INFO: Pst files for design FMC_TLU_LEDS_PMT_PWR successfully written.
system time 0
user time 0
Cadence/worklib/fmc_tlu_leds_pmt_pwr/sch_1/page1.cpc
View file @ 28520943
......@@ -169,6 +169,15 @@
#ISCELL
cnpower p3v3 *
page1_i156
#CELL
cds_special link-0603-open *
page1_i157
#CELL
cds_special link-0603-open *
page1_i158
#CELL
cnpassive rsmd0603 *
page1_i159
#ISCELL
standard gnd_signal *
page1_i47
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/sch_1/page2.cpc
View file @ 28520943
......@@ -250,6 +250,39 @@
#ISCELL
cnpower p3v3 *
page2_i205
#CELL
cnpassive rsmd0603 *
page2_i206
#CELL
cnpassive rsmd0603 *
page2_i207
#ISCELL
standard gnd_signal *
page2_i208
#CELL
cnmemory 24aa025e48 *
page2_i209
#CELL
cnpassive capcersmdcl2 *
page2_i210
#ISCELL
cnpower p3v3 *
page2_i211
#CELL
cnpassive rsmd0603 *
page2_i212
#CELL
cnpassive rsmd0603 *
page2_i213
#CELL
cnpassive rsmd0603 *
page2_i214
#ISCELL
standard gnd_signal *
page2_i215
#CELL
cnpassive rsmd0603 *
page2_i216
#CELL
cnpassive rsmd0603 *
page2_i3
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/sch_1/pc.db
View file @ 28520943
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 17.2-2016 p007 (v17-2-50G) 3/10/2016 on Fri Feb 02 16:19:22 2018
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 17.2-2016 S028 (3668086) 10/9/2017 on Wed May 9 13:00:01 2018
#ISCELL
bris_cds_standard a3-2000 *
*
......@@ -170,6 +170,15 @@
#ISCELL
cnpower p3v3 *
page1_i156
#CELL
cds_special link-0603-open *
page1_i157
#CELL
cds_special link-0603-open *
page1_i158
#CELL
cnpassive rsmd0603 *
page1_i159
#ISCELL
standard gnd_signal *
page1_i47
......@@ -479,6 +488,39 @@
#ISCELL
cnpower p3v3 *
page2_i205
#CELL
cnpassive rsmd0603 *
page2_i206
#CELL
cnpassive rsmd0603 *
page2_i207
#ISCELL
standard gnd_signal *
page2_i208
#CELL
cnmemory 24aa025e48 *
page2_i209
#CELL
cnpassive capcersmdcl2 *
page2_i210
#ISCELL
cnpower p3v3 *
page2_i211
#CELL
cnpassive rsmd0603 *
page2_i212
#CELL
cnpassive rsmd0603 *
page2_i213
#CELL
cnpassive rsmd0603 *
page2_i214
#ISCELL
standard gnd_signal *
page2_i215
#CELL
cnpassive rsmd0603 *
page2_i216
#CELL
cnpassive rsmd0603 *
page2_i3
......
Cadence/worklib/fmc_tlu_toplevel_e/physical/crosssection_fmc_tlu_v1e_148.out 0 → 100755
View file @ 28520943
Cross Section Report
P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_148.brd
Fri May 19 14:51:02 2017
Design Cross Section
Subclass Name,Type,Material,Thickness (MM),Conductivity (mho/cm),Dielectric Constant,Loss Tangent,Negative Artwork,Shield,Width (MM),Single Impedance (ohm),Coupling Type,Spacing (MM),Differential Impedance (ohm),Unused Pin Pad Suppression,Unused Via Pad Suppression
,SURFACE,AIR,,0,1,0,,,,,,,,,
TOP,CONDUCTOR,COPPER,0.0305,595900,1,0,,,0.17,139.84,EDGE,0.15,128.21,,
,DIELECTRIC,FR-4,0.22,0,4.5,0.035,,,,,,,,,
L2,CONDUCTOR,COPPER,0.0305,595900,1,0.035,,,0.17,113.33,NONE,,,,
,DIELECTRIC,FR-4,0.3,0,4.5,0.035,,,,,,,,,
L3,CONDUCTOR,COPPER,0.0305,595900,1,0.035,,,0.17,100.74,EDGE,0.15,100.04,,
,DIELECTRIC,FR-4,0.22,0,4.5,0.035,,,,,,,,,
L4,CONDUCTOR,COPPER,0.0305,595900,1,0.035,,,0.17,74.375,NONE,,,,
,DIELECTRIC,FR-4,0.3,0,4.5,0.035,,,,,,,,,
L5,PLANE,COPPER,0.0305,595900,4.5,0.035,,Yes,,,,,,,
,DIELECTRIC,FR-4,0.22,0,4.5,0.035,,,,,,,,,
BOTTOM,CONDUCTOR,COPPER,0.0305,595900,1,0,,,0.17,75.003,EDGE,0.15,113.32,,
,SURFACE,AIR,,0,1,0,,,,,,,,,
Total Thickness: 1.443 MM
Cadence/worklib/fmc_tlu_toplevel_e/physical/crosssection_fmc_tlu_v1e_150.out 0 → 100755
View file @ 28520943
Cross Section Report
P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd
Tue Jan 30 16:27:19 2018
Design Cross Section
Subclass Name,Type,Material,Thickness (MM),Tol +,Tol -,Conductivity (mho/cm),Dielectric Constant,Loss Tangent,Negative Artwork,Shield,Width (MM),Unused Pin Pad Suppression,Unused Via Pad Suppression
,SURFACE,AIR,,,,0,1,0,,,,,
TOP,CONDUCTOR,COPPER,0.018,0,0,595900,1,0,,,0.1700,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
L2,PLANE,COPPER,0.035,0,0,595900,1,0.035,,Yes,,,
,DIELECTRIC,FR-4,0.36,0,0,0,4.5,0.035,,,,,
L3,CONDUCTOR,COPPER,0.035,0,0,595900,1,0.035,,,0.1700,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
L4,CONDUCTOR,COPPER,0.035,0,0,595900,1,0.035,,,0.1700,,
,DIELECTRIC,FR-4,0.36,0,0,0,4.5,0.035,,,,,
L5,PLANE,COPPER,0.035,0,0,595900,4.5,0.035,,Yes,,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
BOTTOM,CONDUCTOR,COPPER,0.018,0,0,595900,1,0,,,0.1700,,
,SURFACE,AIR,,,,0,1,0,,,,,
Total Thickness: 1.616 MM
Cadence/worklib/fmc_tlu_toplevel_e/physical/crosssection_fmc_tlu_v1e_151.out 0 → 100755
View file @ 28520943
Cross Section Report
P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_151.brd
Wed Jan 31 13:41:36 2018
Design Cross Section
Subclass Name,Type,Material,Thickness (MM),Tol +,Tol -,Conductivity (mho/cm),Dielectric Constant,Loss Tangent,Negative Artwork,Shield,Width (MM),Unused Pin Pad Suppression,Unused Via Pad Suppression
,SURFACE,AIR,,,,0,1,0,,,,,
TOP,CONDUCTOR,COPPER,0.018,0,0,595900,1,0,,,0.1700,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
L2,PLANE,COPPER,0.035,0,0,595900,1,0.035,,Yes,,,
,DIELECTRIC,FR-4,0.36,0,0,0,4.5,0.035,,,,,
L3,CONDUCTOR,COPPER,0.035,0,0,595900,1,0.035,,,0.1700,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
L4,CONDUCTOR,COPPER,0.035,0,0,595900,1,0.035,,,0.1700,,
,DIELECTRIC,FR-4,0.36,0,0,0,4.5,0.035,,,,,
L5,PLANE,COPPER,0.035,0,0,595900,4.5,0.035,,Yes,,,
,DIELECTRIC,FR-4,0.24,0,0,0,4.5,0.035,,,,,
BOTTOM,CONDUCTOR,COPPER,0.018,0,0,595900,1,0,,,0.1700,,
,SURFACE,AIR,,,,0,1,0,,,,,
Total Thickness: 1.616 MM
Cadence/worklib/fmc_tlu_toplevel_e/physical/dfa_fmc_tlu_v1e_148.out 0 → 100755
View file @ 28520943
//
// Allegro DFA Constraints table
// Last modified on Friday, May 19, 2017
//
DFA_TABLE_NAME=dfa_fmc_tlu_v1e_148.out
READONLY=NO
UNITS=MILS
//
//
TAB=Top
ENDTAB
TAB=Bottom
ENDTAB
Cadence/worklib/fmc_tlu_toplevel_e/physical/dfa_fmc_tlu_v1e_150.out 0 → 100755
View file @ 28520943
//
// Allegro DFA Constraints table
// Last modified on Tuesday, January 30, 2018
//
DFA_TABLE_NAME=dfa_fmc_tlu_v1e_150.out
READONLY=NO
UNITS=MILS
//
//
TAB=Top
ENDTAB
TAB=Bottom
ENDTAB
Cadence/worklib/fmc_tlu_toplevel_e/physical/dfa_fmc_tlu_v1e_151.out 0 → 100755
View file @ 28520943
//
// Allegro DFA Constraints table
// Last modified on Wednesday, January 31, 2018
//
DFA_TABLE_NAME=dfa_fmc_tlu_v1e_151.out
READONLY=NO
UNITS=MILS
//
//
TAB=Top
ENDTAB
TAB=Bottom
ENDTAB
Cadence/worklib/fmc_tlu_toplevel_e/physical/layers_fmc_tlu_v1e_148.out 0 → 100755
View file @ 28520943
A!LAYER_SORT!LAYER_SUBCLASS!LAYER_ARTWORK!LAYER_USE!LAYER_CONDUCTOR!LAYER_DIELECTRIC_CONSTANT!LAYER_ELECTRICAL_CONDUCTIVITY!LAYER_MATERIAL!LAYER_SHIELD_LAYER!LAYER_THERMAL_CONDUCTIVITY!LAYER_THICKNESS!LAYER_TYPE!LAYER_LOSS_TANGENT!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_148.brd!Fri May 19 14:51:08 2017!-500.0000!-500.0000!500.0000!500.0000!0.0001!millimeters!FMC_TLU_TOPLEVEL_E!56.811024 mil!6!OUT OF DATE!
S!000!!!!NO!1!0 mho/cm!AIR!!0 w/cm-degC!0 mil!SURFACE!0!
S!001!TOP!POSITIVE!!YES!1.000!595900.000000 mho/cm!COPPER!NO!0 w/cm-degC!1.200787 mil!CONDUCTOR!0!
S!002!!!!NO!4.5!0 mho/cm!FR-4!!0 w/cm-degC!8.661417 mil!DIELECTRIC!0.035!
S!003!L2!POSITIVE!!YES!1.000!595900.000000 mho/cm!COPPER!NO!0.012 w/cm-degC!1.200787 mil!CONDUCTOR!0.03500!
S!004!!!!NO!4.500!0 mho/cm!FR-4!!0.012 w/cm-degC!11.811024 mil!DIELECTRIC!0.03500!
S!005!L3!POSITIVE!!YES!1.000!595900.000000 mho/cm!COPPER!NO!0.012 w/cm-degC!1.200787 mil!CONDUCTOR!0.03500!
S!006!!!!NO!4.500!0 mho/cm!FR-4!!0.012 w/cm-degC!8.661417 mil!DIELECTRIC!0.03500!
S!007!L4!POSITIVE!!YES!1.000!595900.000000 mho/cm!COPPER!NO!0.012 w/cm-degC!1.200787 mil!CONDUCTOR!0.03500!
S!008!!!!NO!4.500!0 mho/cm!FR-4!!0.012 w/cm-degC!11.811024 mil!DIELECTRIC!0.03500!
S!009!L5!POSITIVE!EMBEDDED_PLANE!YES!4.500!595900.000000 mho/cm!COPPER!YES!0.012 w/cm-degC!1.200787 mil!PLANE!0.03500!
S!010!!!!NO!4.500!0 mho/cm!FR-4!!0.012 w/cm-degC!8.661417 mil!DIELECTRIC!0.03500!
S!011!BOTTOM!POSITIVE!!YES!1.000!595900.000000 mho/cm!COPPER!NO!0 w/cm-degC!1.200787 mil!CONDUCTOR!0!
S!012!!!!NO!1!0 mho/cm!AIR!!0 w/cm-degC!0 mil!SURFACE!0!
Cadence/worklib/fmc_tlu_toplevel_e/physical/layers_fmc_tlu_v1e_150.out 0 → 100755
View file @ 28520943
A!LAYER_SORT!LAYER_SUBCLASS!LAYER_ARTWORK!LAYER_USE!LAYER_CONDUCTOR!LAYER_DIELECTRIC_CONSTANT!LAYER_ELECTRICAL_CONDUCTIVITY!LAYER_MATERIAL!LAYER_SHIELD_LAYER!LAYER_THERMAL_CONDUCTIVITY!LAYER_THICKNESS!LAYER_TYPE!LAYER_LOSS_TANGENT!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd!Tue Jan 30 16:27:22 2018!-500.0000!-500.0000!500.0000!500.0000!0.0001!millimeters!FMC_TLU_TOPLEVEL_E!63.622047 mil!6!OUT OF DATE!
S!000000!!!!NO!1.000000!0 mho/cm!AIR!NO!!0 mil!SURFACE!0!
S!000001!TOP!POSITIVE!!YES!1.000000!595900 mho/cm!COPPER!NO!!0.708661 mil!CONDUCTOR!0!
S!000002!!!!NO!4.500000!0 mho/cm!FR-4!!!9.448819 mil!DIELECTRIC!0.035!
S!000003!L2!POSITIVE!EMBEDDED_PLANE!YES!1.000000!595900 mho/cm!COPPER!YES!!1.377953 mil!PLANE!0.035!
S!000004!!!!NO!4.500000!0 mho/cm!FR-4!!!14.173228 mil!DIELECTRIC!0.035!
S!000005!L3!POSITIVE!!YES!1.000000!595900 mho/cm!COPPER!NO!!1.377953 mil!CONDUCTOR!0.035!
S!000006!!!!NO!4.500000!0 mho/cm!FR-4!!!9.448819 mil!DIELECTRIC!0.035!
S!000007!L4!POSITIVE!!YES!1.000000!595900 mho/cm!COPPER!NO!!1.377953 mil!CONDUCTOR!0.035!
S!000008!!!!NO!4.500000!0 mho/cm!FR-4!!!14.173228 mil!DIELECTRIC!0.035!
S!000009!L5!POSITIVE!EMBEDDED_PLANE!YES!4.500000!595900 mho/cm!COPPER!YES!!1.377953 mil!PLANE!0.035!
S!000010!!!!NO!4.500000!0 mho/cm!FR-4!!!9.448819 mil!DIELECTRIC!0.035!
S!000011!BOTTOM!POSITIVE!!YES!1.000000!595900 mho/cm!COPPER!NO!!0.708661 mil!CONDUCTOR!0!
S!000012!!!!NO!1.000000!0 mho/cm!AIR!NO!!0 mil!SURFACE!0!
Cadence/worklib/fmc_tlu_toplevel_e/physical/regions_fmc_tlu_v1e_148.out 0 → 100755
View file @ 28520943
A!CLASS!SUBCLASS!RECORD_TAG!GRAPHIC_DATA_NAME!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!REGION_NAME!
Cadence/worklib/fmc_tlu_toplevel_e/physical/regions_fmc_tlu_v1e_150.out 0 → 100755
View file @ 28520943
A!CLASS!SUBCLASS!RECORD_TAG!GRAPHIC_DATA_NAME!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!REGION_NAME!
Cadence/worklib/fmc_tlu_toplevel_e/physical/regions_fmc_tlu_v1e_151.out 0 → 100755
View file @ 28520943
A!CLASS!SUBCLASS!RECORD_TAG!GRAPHIC_DATA_NAME!GRAPHIC_DATA_1!GRAPHIC_DATA_2!GRAPHIC_DATA_3!GRAPHIC_DATA_4!GRAPHIC_DATA_5!GRAPHIC_DATA_6!GRAPHIC_DATA_7!GRAPHIC_DATA_8!GRAPHIC_DATA_9!GRAPHIC_DATA_10!REGION_NAME!
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