Commit 5682c9c6 authored by David Cussans's avatar David Cussans

Rearranging documentation files

parents

Too many changes to show.

To preserve performance only 1000 of 1000+ files are displayed.

DEFINE fmc_tlu_v1_lib worklib
# Include EUDET TLU to get hold of pin-out
DEFINE uob_hep_pc036a_lib pc042a_lib
INCLUDE $RAL_CDSLIB/cds.lib
INCLUDE $BRIS_CDSLIB/cds.lib
INCLUDE $CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/cds.lib
INCLUDE $CONCEPT_INST_DIR/share/cdssetup/cds.lib
\o COPYRIGHT ? 1997-2004 CADENCE DESIGN SYSTEMS INC. ALL RIGHTS RESERVED.
\o This Cadence Design Systems program and online documentation are
\o proprietary/confidential information and may be disclosed/used only
\o as authorized in a license agreement controlling such use and disclosure.
\o
\o RESTRICTED RIGHTS NOTICE (SHORT FORM)
\o Use/reproduction/disclosure is subject to restriction
\o set forth at FAR 1252.227-19 or its equivalent.
\o Loading globalChange.cxt
\o Loading cnServ.cxt
INFO(COPYPROJ-87): Compiling a list of read-only files.
SUCCESS(COPYPROJ-88): Read-only files list compiled successfully.
INFO(COPYPROJ-81): Executing csnetlister -proj fmc_tlu_v1.cpm.
SUCCESS(COPYPROJ-83): Successfully executed csnetlister.
Source Info :
=============
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1.cpm
Library : fmc_tlu_v1_lib
Design : fmc_tlu_toplevel
Destination Info :
==================
Project : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1a.cpm
Library : fmc_tlu_v1_lib
Design : fmc_tlu_toplevel_b
INFO(COPYPROJ-17): Copying old design hierarchy.
SUCCESS(COPYPROJ-18): Copied old design hierarchy.
INFO(COPYPROJ-44): Updating variant view.
SUCCESS(COPYPROJ-45): Variants view updated successfully.
INFO(COPYPROJ-64): Updating design data.
SUCCESS(COPYPROJ-65): Design data updated successfully.
SUCCESS(COPYPROJ-48): Pxl state file in packaged view updated successfully.
INFO(COPYPROJ-40): Updating opf view.
SUCCESS(COPYPROJ-41): Opf view updated successfully.
INFO(COPYPROJ-61): Updating constraints view.
SUCCESS(COPYPROJ-62): Constraints view updated successfully.
INFO(COPYPROJ-84): Executing nconcepthdl -proj "fmc_tlu_v1a.cpm" -scr "./cp_script.scr" -log "./cp_log.log".
SUCCESS(COPYPROJ-86): Successfully executed nconcepthdl.
INFO(COPYPROJ-91): Starting to set back the read-only flag.
SUCCESS(COPYPROJ-92): Read-only flag set successfully for all files.
SUCCESS(COPYPROJ-67): Copy Project Success.
{ Machine generated file created by SPI }
{ Last modified was 09:55:17 Thursday, September 19, 2013 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_cfd/physical'
design_name 'fmc_tlu_cfd'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cds_standard' 'cn100e' 'pc017a_lib'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_cfd/physical'
END_GLOBAL
START_CONCEPTHDL
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
feedback 'ALLEGRO'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'ON'
gen_subdesign 'fmc_tlu_cfd'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_cfd_07.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 13:45:22 Friday, June 14, 2013 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_toplevel/physical'
design_name 'fmc_tlu_toplevel'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_toplevel/physical'
trapezoidal_angle_in_degree '90.000000'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'pc042b_vsupply5v'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1_45.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel/bom/fmc_mtlu_ bom.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 13:02:03 Thursday, October 10, 2013 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_toplevel_b/physical'
design_name 'fmc_tlu_toplevel_b'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_toplevel_b/physical'
trapezoidal_angle_in_degree '90.000000'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_63.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_b/bom/fmc_tlu_v1a.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 16:30:38 Thursday, September 26, 2013 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_vsupply5v/physical'
design_name 'fmc_tlu_vsupply5v'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_vsupply5v/physical'
trapezoidal_angle_in_degree '90.000000'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
feedback 'ALLEGRO'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN 'fmc_tlu_vsupply5v'
FORCE_SUBDESIGN
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_vsupply5v_02.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_vsupply5v/bom/fmc_mtlu_ bom.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 10:55:08 Wednesday, June 19, 2013 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_to_fmc_adaptor/physical'
design_name 'fmc_to_fmc_adaptor'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_to_fmc_adaptor/physical'
trapezoidal_angle_in_degree '90.000000'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'pc042b_vsupply5v'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_to_fmc_adaptor_01.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_to_fmc_adaptor/bom/fmc_mtlu_ bom.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
// generated by NetAssembler Version 15.51-s002 12-Apr-2006
// on Wed Jun 13 08:32:56 2007
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire agnd;
wire avdd;
wire dgnd;
wire dvdd;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Thu Jun 30 18:39:08 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
supply1 supply_1;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Mon May 23 17:44:33 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
wire p1v25a;
wire p1v25d;
wire p2v5b;
endmodule
// generated by NetAssembler Version 16.2-p001 (v16-2-57A) 9/30/2008
// on Mon Nov 15 13:04:58 2010
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
`ifdef XILINX
`include "C:/Xilinx92i/cadence/data/global.v"
`endif
// Verilog global signals module
wire gnd_signal;
wire p1v25a;
wire p1v25d;
wire p2v5;
wire p2v5b;
wire p3v3;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Tue Jun 21 14:55:37 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
wire p1v25a;
wire p1v25d;
wire p2v5;
wire p2v5b;
wire p3v3;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Tue Jun 28 17:12:51 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
wire p1v25a;
wire p1v25c;
wire p1v25d;
wire p2v5b;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Fri Jun 3 10:24:28 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Mon Jun 13 09:29:16 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Fri Jun 3 10:48:20 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Tue Jun 28 15:54:16 2011
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
endmodule
// generated by NetAssembler Version 16.1-S5 (v16-1-53AH) 7/2/2008
// on Fri Feb 26 15:56:39 2010
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
`ifdef VAN
wire gnd;
`else
supply0 gnd;
`endif
`ifdef VAN
wire vcc;
`else
supply1 vcc;
`endif
endmodule
// generated by NetAssembler Version 16.1-S5 (v16-1-53AH) 7/2/2008
// on Thu Feb 25 16:02:21 2010
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
`ifdef VAN
wire gnd;
`else
supply0 gnd;
`endif
`ifdef VAN
wire vcc;
`else
supply1 vcc;
`endif
endmodule
// generated by NetAssembler Version 16.2-p001 (v16-2-57A) 9/30/2008
// on Fri Jul 16 11:51:20 2010
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
`ifdef XILINX
`include "C:/Xilinx92i/cadence/data/global.v"
`endif
// Verilog global signals module
wire avdd;
`ifdef VAN
wire gnd;
`else
supply0 gnd;
`endif
wire p2v5;
wire p3v3;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Thu Apr 12 14:57:33 2012
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
wire p1v5a;
wire p2v5;
wire p3v3;
wire p5v;
supply1 supply_1;
endmodule
// generated by NetAssembler Version 16.3-p002 (v16-3-85A) 10/19/2009
// on Mon May 14 10:08:23 2012
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
`ifdef XILINX
`include "C:/Xilinx92i/cadence/data/global.v"
`endif
// Verilog global signals module
wire gnd_power;
wire gnd_signal;
wire p1v5a;
wire p2v5;
wire p3v3;
wire p5v;
supply1 supply_1;
endmodule
// generated by NetAssembler Version 16.3-P2 (v16-3-85A) 10/19/2009
// on Wed May 16 13:39:32 2012
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire gnd_signal;
endmodule
// generated by NetAssembler Version 15.20-s002 19-Aug-2004
// on Fri Apr 15 10:34:12 2005
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire v125;
wire vdd;
wire vss;
endmodule
// generated by NetAssembler Version 15.20-s002 19-Aug-2004
// on Wed Jul 6 08:42:09 2005
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire v125;
wire vdd;
wire vss;
endmodule
-- pcdb file, Rev:1.0 written by VAN 06.01-b01 on Jul 2, 2010 17:40:45
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