Commit 71be7a85 authored by David Cussans's avatar David Cussans

Checking in files before taking branch for firmware work

parent 63572b2e
{ Machine generated file created by SPI }
{ Last modified was 14:17:26 Wednesday, December 06, 2017 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
merge_ppt 'OFF'
view_pcb './worklib/fmc_tlu_leds_pmt_pwr/physical'
design_name 'fmc_tlu_leds_pmt_pwr'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special' 'cnmech' 'bris_cds_discrete' 'bris_cds_pld'
temp_dir 'temp'
cpm_version '16.3'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_leds_pmt_pwr/physical'
session_name 'ProjectMgr29088'
expand_with_errors 'OFF'
trapezoidal_angle_in_degree '90.000000'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'C4' 'c12' 'r2' 'C9' 'C1'
AUTO_UPDATE_DEFAULT_MODELS 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME '\\its-zonedprint.cse.bris.ac.u'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_clock_gen' 'fmc_tlu_hdmi_dut_connector' 'fmc_tlu_threshold_discriminator_dual' 'fmc_tlu_vsupply5v'
f2b_overwrite_constraints 'OFF'
b2f_overwrite_constraints 'OFF'
import_constraints_only_feedback 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '1'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_leds_pmt_pwr_09.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'YES'
show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_leds_pmt_pwr/bom/BOM_summary.csv'
last_template_file 'Z:/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Comma ,'
use_filters '0'
last_callout_file ''
last_variant ''
GEN_HIER_BOM '0'
END_BOMHDL
START_ERCDX
pin_direction_check 'OFF'
io_check 'OFF'
load_check 'OFF'
connect_check 'OFF'
END_ERCDX
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 10:38:54 Tuesday, September 26, 2017 }
{ Last modified was 13:53:54 Wednesday, January 10, 2018 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_TOOLS
SigXplore 'sigxp' '' '' '&SigXplorer' 'NO' '0' 'YES' 'NO'
END_TOOLS
START_PROJECTMGR
LastFlow 'Board Design'
END_PROJECTMGR
START_GLOBAL
merge_ppt 'OFF'
view_pcb './worklib/fmc_tlu_toplevel_e/physical'
......@@ -28,16 +36,15 @@ DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'CN1*' 'CN2*' 'CLK_IO_2' 'CLK_FROM_FPGA*' 'DATA_FROM_CDR*'
PAPER_SIZE '8'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'PDF Writer - bioPDF'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
SEARCH_HISTORY 'CN1*' 'CN2*' 'CLK_IO_2' 'CLK_FROM_FPGA*' 'DATA_FROM_CDR*'
END_CONCEPTHDL
START_PKGRXL
......
#!/usr/bin/perl -w
#
# Script to process netlist from pc051b 64-channel ADC board and
# print out Vivado constraint file
#
# David Cussans, October 2016
#
use strict;
my $busname;
my $busidx;
my @fields;
my $netName;
my $fpgaPin;
my $idx;
while (<>){
chomp ;
@fields = split "," , $_;
$netName = $fields[4];
$fpgaPin = $fields[11];
$idx = $fields[5];
# print "$netName $fpgaPin $idx \n";
if ($netName =~ /(\w+)<(\d+)>/) {
($busname , $busidx) = ( $1,$2);
# print "Bus! base = $busname , index = $busidx , pin = $fpgaPin\n";
print "set_property PACKAGE_PIN $fpgaPin [get_ports {".$busname."[$busidx]}]\n";
} else {
# print "NetName = $netName , pin = $fpgaPin\n";
print "set_property PACKAGE_PIN $fpgaPin [get_ports {$netName}]\n";
}
#print $netName;
#print $fpgaPin;
#print "\n\n";
}
TITLE: Bill of Materials
DATE: 05/31/2017
DESIGN: fmc_tlu_toplevel_e
TEMPLATE: P:\cad\tools\cadence_templates\spreadsheet-format.bom
CALLOUT: bom.callouts
Part Name,Ref Des,Qty,PART_NUMBER,PART_DESCRIPTION,OL_COMMENTS,KL_COMMENTS,PL_COMMENTS,Do Not Fit
1-HOLE_0-8-BASE,"LK1_9,LK2_9,LK3_9,LK4_9",4,?,0.8mm Hole,?,?,?,?
24AA025E48T-I/SN,IC5,1,24AA025E48T-I/SN,?,?,?,?,?
AD5665RBRUZ-1,"IC1,IC2",2,AD5665RBRUZ-1,?,?,?,?,?
ADN2814ACPZ,IC8,1,ADN2814ACPZ,?,?,?,?,?
ASP-134606-01,J4,1,ASP-134606-01,?,?,?,?,?
BF-50.000MBE-T,QZ1_9,1,BF-100.000MBE-T,?,?,?,?,?
"CAPCERSMDCL2_0402-100NF,16V_GEN","C11_9,C12_9,C14_9,C15_9,C17_9,C19_9,C22_9,C23_9,C25_9,C37_9",10,CC0402_100NF_16V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0402-10NF,16V_GEN","C31_9,C32_9,C33_9,C34_9,C35_9,C36_9",6,CC0402_10NF_16V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-1.0NF,50V","C31,C33,C34",3,CC0603_1NF_50V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-1.0UF,6.3V","C5_6,C5_7,C5_8,C6_6,C6_7,C6_8,C8_6,C8_7,C8_8,C14_6,C14_7,C14_8,C47,C48,C49,C50,C51,C52",18,CC0603_1UF_6V3_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_0603-100NF,16V","C1_1,C1_2,C1_3,C1_4,C1_6,C1_7,C1_8,C1_9,C2_1,C2_2,C2_3,C2_4,C2_6,C2_7,C2_8,C2_9,C3,C3_1,C3_2,C3_3,C3_4,C3_9,C4_1,C4_2,C4_3,C4_4,C4_9,C5_1,C5_2,C5_3,C5_4,C5_9,C6_9,C7,C7_1,C7_2,C7_3,C7_4,C7_6,C7_7,C7_8,C8,C9,C9_1,C9_2,C9_3,C9_4,C9_6,C9_7,C9_8,C10,C10_1,C10_2,C10_3,C10_4,C10_6,C10_7,C10_8,C10_9,C11,C11_1,C11_2,C11_3,C11_4,C11_6,C11_7,C11_8,C12,C12_1,C12_2,C12_3,C12_4,C12_6,C12_7,C12_8,C13_1,C13_2,C13_3,C13_4,C13_6,C13_7,C13_8,C14,C15,C16,C17,C18_9,C19,C20,C20_9,C23,C24,C25,C26,C27_9,C28_9,C29_9,C30_9,C37,C38,C38_9,C39,C39_9,C40,C40_9,C41,C41_9,C42,C43,C70",110,CC0603_100NF_16V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-100NF,50V_X7R","C32,C35,C36",3,CC0603_100NF_50V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-10NF,50V","C3_6,C3_7,C3_8,C4_6,C4_7,C4_8",6,CC0603_10NF_50V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-10NF,50V_X7R","C21,C22",2,CC0603_10NF_50V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0603-10UF,6.3V","C8_9,C9_9,C16_9,C24_9,C26_9",5,CC0603_10UF_6V3_20%_X5R,?,?,?,?,?
"CAPCERSMDCL2_0603-10UF_X5R,6.3V",C13,1,CC0603_10UF_6V3_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_0603-1UF,16V","C1,C2,C4,C5,C6,C44,C45,C46",8,CC0603_1UF_16V_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_0805-1NF,200V_X7R","C27,C28,C29,C30",4,CC0805_1NF_200V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0805-22UF,6.3V","C13_9,C21_9",2,CC0805_22UF_6V3_15%_X7R,?,?,?,?,?
"CAPCERSMDCL2_0805-4.7UF,10V","C6_1,C6_2,C6_3,C6_4,C8_1,C8_2,C8_3,C8_4,C9_5,C10_5,C11_5,C12_5",12,GRM21BF51A475ZA01,?,?,?,?,?
"CAPCERSMDCL2_0805-470NF,25V_GEN",C18,1,CC0805_470NF_25V_10%_X7R,?,?,?,?,?
"CAPCERSMDCL2_1210-10UF,10V_GEN",C7_9,1,CC1210_10UF_25V_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_1210-22UF,16V","C7_5,C8_5",2,CC1210_22UF_16V_10%_X5R,?,?,?,?,?
"CAPCERSMDCL2_1210-4.7UF,50V","C1_5,C2_5,C3_5,C4_5,C5_5,C6_5",6,CC1210_4.7UF_50V_10%_X7R,?,?,?,?,?
"CAPN4I-1UF,16V,X5R,GNM21","CN1_1,CN1_2,CN1_3,CN1_4,CN2_9",5,GNM214B11C105MA01D,?,?,?,?,?
"COMMON_MODE_LINE_FILTER_4312-744231091,90OHM","L1_1,L1_2,L1_3,L1_4,L1_9,L2_1,L2_2,L2_3,L2_4,L2_9,L3_1,L3_2,L3_3,L3_4,L3_9,L4_1,L4_2,L4_3,L4_4,L4_9,L8_9",21,744231091,?,?,?,?,?
CON16P-MTLW-108-07-L-D-250,J1,1,MTLW-108-07-L-D-250,?,?,?,?,?
CON19P-HDMI-19-01-X-SM,"J1_1,J1_2,J1_3,J1_4",4,HDMI-19-01-X-SM,?,?,?,?,?
CON20P_SFP-1888247-1,J2,1,1888247-1,?,?,?,?,?
CON3P-SIL254D,"J1_9,J3",2,MTLW-103-07-L-S-250,?,?,?,?,?
DS92001TLD,"IC1_9,IC2_9,IC3_9,IC4_9,IC5_9,IC7_9",6,DS92001TLD,?,?,?,?,?
"FERRITE_C0805-LI0805H121R-10,LI0805H121R-10","L5_9,L6_9,L7_9",3,LI0805H121R-10,?,?,?,?,?
"FERRITE_SMD-7427921,WURTH","L2_5,L3_5",2,7427921,?,?,?,?,?
"FERRITE_SMD-BLM41P800S,MURATA",L1_5,1,08.11.BLM41P800S,?,?,?,?,?
HBAT-540C,"D1_6,D1_7,D1_8,D2_6,D2_7,D2_8",6,HBAT-540C,?,?,?,?,?
INDUCTANCE_LQH32C_23-4.7UH,"L1,L2",2,LQH32CN4R7M23,?,?,?,?,?
LED1-597_GREEN,"LD1,LD2,LD3",3,597-3301-502F,?,?,?,?,?
"LP38692SD_WSON-1.8V,TEXAS INSTRUMENTS",U1_9,1,LP38692SD-1.8,"Fixed 1.8V low dropout regulator, 900mA , stable with ceramic capacitors , WSON-6 package",Available from Farnell 2492289,?,?,?
"LP5951_SOT23-5-1.3V,TEXAS INSTRUMENTS",U1,1,LP5951MF-1.3,"1.3V, 150mA Low Dropout Regulator",Farnell 1312651,-,-,?
LT1129CST-5_SOT223-LINEAR,VR1_5,1,Linear Technology LT1129CST-5,"700mA, 5V LDO Regulator",Farnell 1663375,-,-,?
LT1175_SOT_223,REG1_5,1,Farnell,500mA Negative low dropout Micropower Regulator,-,-,-,?
LTM8047EY#PBF,"RG1_5,RG2_5",2,LTM8047EY#PBF,?,?,?,?,?
MAX9601_TSSOP,"IC1_6,IC1_7,IC1_8",3,MAX9601EUP,?,?,?,?,?
NBSG53AMNGMOD,IC9,1,NBSG53AMNGMOD,?,?,?,?,?
OPA4277UA,"IC3,IC4",2,OPA4277UA,?,?,?,?,?
PCA9517DGKR,IC10,1,PCA9517DGKR,?,?,?,?,?
PCA9539PW,"IC6,IC7",2,PCA9539PW,?,?,?,?,?
PCOAX-PLEMO00C,"PX1,PX2,PX3,PX4,PX5,PX6",6,EPK.00.250.NTN,?,?,?,?,?
PLEMO2CI-EPG.00.302.NLN,LM1_9,1,EPG.00.302.NLN,?,?,?,?,?
PRTR5V0U4Y,"D1_1,D1_2,D1_3,D1_4,D2_1,D2_2,D2_3,D2_4",8,PRTR5V0U4Y,?,?,?,?,?
"RES_ARRAY_X4_1206_TC164-47,1%","RN1_1,RN1_2,RN1_3,RN1_4,RN2_1,RN2_2,RN2_3,RN2_4,RN3_9",9,TC164-FR-##47RL,?,?,?,?,?
"RSMD0402_1/16W-0R0,1%","R52,R54,R55,R69,R71,R72,R73",7,R0402_0R_1%_0.063W_100PPM,?,?,?,?,?
"RSMD0603_-00,","R2,R3,R4,R5,R18,R19,R20,R21,R32,R35,R43,R44,R60,R62,R64,R67,R68,R70",18,R0603_00_JUMPER,?,?,?,?,?
"RSMD0603_1/10W-100,1%","R1_9,R2_9,R3_6,R3_7,R3_8,R3_9,R4_6,R4_7,R4_8,R4_9,R9_9,R10_9,R25_9,R26_9,R36",15,R0603_100R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-10K,1%","R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16,R17",12,R0603_10K_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-150,1%","R45,R46",2,R0603_150R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-1K,1%","R1,R5_9,R11_9,R13_9,R14_9,R15_9,R16_9,R17_9,R18_9,R20_9,R21_9,R22_9,R23_9",13,R0603_1K_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-2.2K,1%","R39,R66,R74,R75",4,R0603_2K2_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-2K,1%","R40,R41,R42",3,R0603_2K_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-3.3,1%",R1_5,1,R0603_3R3_1%_0.1W_200PPM,?,?,?,?,?
"RSMD0603_1/10W-4.7K,1%","R6_9,R26,R27,R28,R29,R30,R31,R47,R48,R49,R50,R51",12,R0603_4K7_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-47,1%","R76,R77,R78,R79,R80,R81,R82,R83",8,R0603_47R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-51,1%","R1_1,R1_2,R1_3,R1_4,R2_1,R2_2,R2_3,R2_4",8,R0603_51R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-6.19K,1%","R2_5,R3_5",2,R0603_6K19_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-75,1%","R9_6,R9_7,R9_8,R10_6,R10_7,R10_8,R11_6,R11_7,R11_8,R12_6,R12_7,R12_8",12,R0603_75R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-82,1%","R22,R23,R24",3,R0603_82R_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/10W-XX,1%","R7_6,R7_7,R7_8,R7_9,R8_6,R8_7,R8_8,R8_9,R25,R34,R37,R38,R53,R61,R63,R65",16,R0603_XX_1%_0.1W_100PPM,?,?,?,?,?
"RSMD0603_1/16W-2K,1%",R33,1,R0603_2K_1%_0.063W_100PPM,?,?,?,?,?
"RSMD0603_1/16W-68,1%","R56,R56_7,R56_8,R57,R57_7,R57_8,R58,R58_7,R58_8,R59,R59_7,R59_8",12,R0603_68R_1%_0.063W_100PPM,?,?,?,?,?
"RSMD0805_125MW-100,1%","R1_6,R1_7,R1_8,R2_6,R2_7,R2_8,R5_6,R5_7,R5_8,R6_6,R6_7,R6_8",12,R0805_100R_1%_0.125W_100PPM,?,?,?,?,?
SFP_CAGE-SP-74737-004,SFP1,1,74737-004,?,?,?,?,?
SI5345A-B-GM,IC8_9,1,Si5345A-B-GM,?,?,?,?,?
SN65MLVD040RGZ,"IC1_1,IC1_2,IC1_3,IC1_4,IC6_9",5,SN65MLVD040RGZ,?,?,?,?,?
SN74AVC2T45DCU,"IC11,IC12",2,SN74AVC2T45DCU,?,?,?,?,?
TPS78633DCQ,"IC2_1,IC2_2,IC2_3,IC2_4",4,TPS78633DCQ,?,?,?,?,?
TP_HOLE-0.8MM,"TP1,TP1_1,TP1_2,TP1_3,TP1_4,TP1_6,TP1_7,TP1_8,TP2,TP2_1,TP2_2,TP2_3,TP2_4,TP2_6,TP2_7,TP2_8,TP3,TP3_1,TP3_2,TP3_3,TP3_4,TP3_6,TP3_7,TP3_8,TP4,TP4_1,TP4_2,TP4_3,TP4_4,TP4_6,TP4_7,TP4_8,TP5,TP5_1,TP5_2,TP5_3,TP5_4,TP5_6,TP5_7,TP5_8,TP6,TP6_1,TP6_2,TP6_3,TP6_4,TP6_6,TP6_7,TP6_8,TP7,TP7_1,TP7_2,TP7_3,TP7_4,TP7_6,TP7_7,TP7_8,TP8,TP8_1,TP8_2,TP8_3,TP8_4,TP8_6,TP8_7,TP8_8,TP9_1,TP9_2,TP9_3,TP9_4,TP10_1,TP10_2,TP10_3,TP10_4,TP11_1,TP11_2,TP11_3,TP11_4,TP12_1,TP12_2,TP12_3,TP12_4",80,TP_HOLE_0.8mm,?,?,?,?,?
USBLC6-2SC6,"D3_1,D3_2,D3_3,D3_4,D3_9",5,USBLC6-2SC6,?,?,?,?,?
TOTAL, ,565, , , , , ,
This diff is collapsed.
\t (00:00:01) allegro 16.6-2015 S079 (v16-6-112GH) Windows 32
\t (00:00:01) Journal start - Fri Oct 27 17:16:11 2017
\t (00:00:01) Host=IT062971 User=phpgb Pid=15236 CPUs=8
\t (00:00:01) CmdLine= allegro -proj P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\fmc_tlu_v1e.cpm -product PCB_design_studio -mpssession phpgb_ProjectMgr10741 -mpshost IT062971
\t (00:00:01) allegro 17.2 P028 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Fri Jan 12 15:02:11 2018
\t (00:00:01) Host=IT062971 User=phpgb Pid=24360 CPUs=8
\t (00:00:01) CmdLine= allegro -proj P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\fmc_tlu_v1e.cpm -product Allegro_performance -mpssession phpgb_ProjectMgr28764 -mpshost IT062971
\t (00:00:01)
(00:00:01) Loading axlcore.cxt
(00:00:01) "LOADING SKILL FILES FROM: C:/Cadence/SPB_16.6/share/local/pcb/skill"
(00:00:01) "FILES LOADED:"
(00:00:01) "align_sym.il"
......@@ -26,12 +27,110 @@
(00:00:01) "moveByRefDef.il"
(00:00:01) "single_pin_net_check.il"
(00:00:01) "DONE"
\t (00:00:02) Opening existing design...
\d (00:00:03) Design opened: P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd
\i (00:00:03) trapsize 5310
\i (00:00:03) trapsize 5241
\i (00:00:03) trapsize 5322
\i (00:00:03) trapsize 5322
\i (00:00:04) generaledit
\i (00:00:07) exit
\t (00:00:07) Journal end - Fri Oct 27 17:16:18 2017
\t (00:00:01) Opening existing design...
\i (00:00:03) fillin yes
\d (00:00:04) Design opened: P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd
\i (00:00:04) trapsize 5476
\i (00:00:05) trapsize 5564
\i (00:00:05) trapsize 5601
\i (00:00:06) etchedit
\i (00:00:08) roam start
\i (00:00:08) roam x 208
\i (00:00:08) roam y -160
\i (00:00:08) roam x 352
\i (00:00:08) roam y -160
\i (00:00:08) roam x 272
\i (00:00:08) roam y -80
\i (00:00:08) roam x 256
\i (00:00:08) roam y -64
\i (00:00:08) roam x 64
\i (00:00:08) roam x -16
\i (00:00:08) roam y 128
\i (00:00:08) roam x -304
\i (00:00:08) roam y 272
\i (00:00:09) roam x -560
\i (00:00:09) roam y 112
\i (00:00:09) roam x -496
\i (00:00:09) roam y 48
\i (00:00:09) roam x -416
\i (00:00:09) roam y 48
\i (00:00:09) roam x -96
\i (00:00:09) roam x -64
\i (00:00:09) roam y -32
\i (00:00:09) roam x -32
\i (00:00:09) roam y -32
\i (00:00:09) roam end
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -25.3800 -1.7443
\i (00:00:10) trapsize 2800
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -25.3239 -2.0243
\i (00:00:10) trapsize 1400
\i (00:00:11) roam start
\i (00:00:11) roam x 144
\i (00:00:11) roam y -16
\i (00:00:11) roam x 192
\i (00:00:11) roam y -32
\i (00:00:11) roam x 80
\i (00:00:11) roam y -16
\i (00:00:11) roam x 16
\i (00:00:11) roam x 48
\i (00:00:11) roam y -16
\i (00:00:11) roam x 48
\i (00:00:11) roam x 16
\i (00:00:11) roam x 80
\i (00:00:11) roam x 96
\i (00:00:11) roam y 16
\i (00:00:11) roam x 64
\i (00:00:11) roam x 48
\i (00:00:11) roam x 48
\i (00:00:12) roam x 48
\i (00:00:12) roam end
\i (00:00:14) xhilite
\i (00:00:14) xrefdes R49
\i (00:00:14) xrefdes R49
\i (00:00:14) xname_flush
\i (00:00:14) trapsize 291
\t (00:00:14) Symbol "R49" highlighted.
\i (00:00:14) done
\i (00:00:14) etchedit
\i (00:00:44) zoom out 1
\i (00:00:44) setwindow pcb
\i (00:00:44) zoom out 201.6711 23.5116
\i (00:00:44) trapsize 581
\i (00:00:45) zoom out 1
\i (00:00:45) setwindow pcb
\i (00:00:45) zoom out 201.6712 23.5116
\i (00:00:45) trapsize 1162
\i (00:00:45) zoom out 1
\i (00:00:45) setwindow pcb
\i (00:00:45) zoom out 201.6712 23.5117
\i (00:00:45) trapsize 2324
\i (00:00:45) zoom out 1
\i (00:00:45) setwindow pcb
\i (00:00:45) zoom out 201.6712 23.5117
\i (00:00:45) trapsize 4648
\i (00:00:46) zoom in 1
\i (00:00:46) setwindow pcb
\i (00:00:46) zoom in 197.7664 16.2601
\i (00:00:46) trapsize 2324
\i (00:00:47) zoom in 1
\i (00:00:47) setwindow pcb
\i (00:00:47) zoom in 197.7664 16.2601
\i (00:00:47) trapsize 1162
\i (00:00:48) drag_start grid 199.9512 24.0230
\i (00:00:48) move
\t (00:00:48) last pick: 199.5000 23.5000
\t (00:00:48) Moving R49 / RSMD0603_1/10W-4.7K,1% / C0603.
\t (00:00:48) Pick new location for the element(s).
\i (00:00:48) drag_stop grid 203.4840 26.3937
\i (00:00:49) etchedit
\i (00:00:51) undo
\i (00:00:51) trapsize 1162
\i (00:00:51) etchedit
\i (00:00:59) exit
\e (00:00:59) Do you want to save the changes you made to fmc_tlu_v1e_150.brd?
\i (00:01:01) fillin no
\t (00:01:02) Journal end - Fri Jan 12 15:03:12 2018
......@@ -4,11 +4,11 @@
( )
( Drawing : fmc_tlu_v1e_150.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Jun 16 16:26:32 2017 )
( Date/Time : Wed Dec 13 12:24:19 2017 )
( )
(---------------------------------------------------------------------)
Layout Name : P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd
Paramfile Name : P:/cad/Paolo_AllegroSettings/ColorScheme.prm
Paramfile Name : P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/tlu_v1e_designParameters_export.prm
......@@ -2,15 +2,15 @@
( )
( Technology File WRITE )
( )
( Drawing : fmc_tlu_v1e_148.brd )
( Drawing : fmc_tlu_v1e_150.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri May 19 14:51:00 2017 )
( Date/Time : Wed Dec 13 12:23:40 2017 )
( )
(---------------------------------------------------------------------)
layout name: P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_148.brd
techfile name: tech_fmc_tlu_v1e_148.out
layout name: P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_v1e_150.brd
techfile name: P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_e/physical/fmc_tlu_e.tcf
......@@ -4,7 +4,7 @@
( )
( Drawing : fmc_tlu_v1e_148.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri May 19 14:32:56 2017 )
( Date/Time : Fri May 19 14:37:07 2017 )
( )
(---------------------------------------------------------------------)
......
......@@ -4,7 +4,7 @@
( )
( Drawing : fmc_tlu_v1e_148.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri May 19 14:37:07 2017 )
( Date/Time : Fri May 19 14:45:26 2017 )
( )
(---------------------------------------------------------------------)
......
......@@ -4,7 +4,7 @@
( )
( Drawing : fmc_tlu_v1e_148.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri May 19 14:45:26 2017 )
( Date/Time : Fri May 19 14:51:00 2017 )
( )
(---------------------------------------------------------------------)
......
fmc_tlu_leds_pmt_pwr
These file describes PCB fabrication and assembly details of a
PCB with LEDS and PMT power for the FMC based AIDA-2020 TLU.
contact: David.Cussans@bristol.ac.uk
tel: 0117 95 46879
0117 33 17199
fax: 0117 925 5624
P.Baesso@bristol.ac.uk
tel: 0117 928 7481
Files produced by Cadence Allegro PE16.6
Artwork:
--------
Format: Gerber RS-274X , parameters described in art_param.txt.
All layers viewed from top
Build:
------
Six Layers as follows:
fmc_tlu_leds_pmt_pwr_L01.art
fmc_tlu_leds_pmt_pwr_L02.art
fmc_tlu_leds_pmt_pwr_L03.art
fmc_tlu_leds_pmt_pwr_L04.art
Suggested build (1.6mm total thickness)
1-2 0.22 mm
2-3 1.0 mm
3-4 0.22 mm
FR4 or similar laminate
35um copper on outers ( after plating )
18um copper on inners
Solder Masks
------------
fmc_tlu_leds_pmt_pwr_SM1.art
fmc_tlu_leds_pmt_pwr_SM4.art
Colour not critical, suggest green. Photo-imagable.
Solderpaste mask
-----------------
fmc_tlu_leds_pmt_pwr_SP1.art
fmc_tlu_leds_pmt_pwr_SP4.art
Silk screen
-----------
fmc_tlu_leds_pmt_pwr_SS1.art
fmc_tlu_leds_pmt_pwr_SS4.art
Colour not critical, suggest white.
Assembly Diagram
-----------------
fmc_tlu_leds_pmt_pwr_AST.art
fmc_tlu_leds_pmt_pwr_ASB.art
Board outline: (Gerber RS-274X)
-------------------------------
fmc_tlu_leds_pmt_pwr_OUTLINE.art
Drill figure: ( illustration of hole sizes and position. Also shows cross-section and overall dimensions )
----------------------------------------------------------------------------------------------------------
fmc_tlu_leds_pmt_pwr_DD.art
Drill information ( Excellon format, described in nc_param.txt )
-----------------
Plated and unplated holes in same file.
fmc_tlu_leds_pmt_pwr_21-1-4.drl
Bill of Materials
-----------------
Three "sheets":
- one line per component type
- one line per component instance ( includes position information of pin-1 )
fmc_tlu_leds_tlu_pwr.xlsx
Component placement
-------------------
placement_pin1.txt
( Position of pin-1 in mm and rotation in degrees of each component )
ODB++ format (PCB and assembly information):
-------------
fmc_tlu_leds_pmt_pwr_21.tgz
DEVICE-TYPE GERBER_RS274X
OUTPUT-UNITS MM
FILM-SIZE 2400000 1600000
FORMAT 3.5
ABORT-ON-ERROR NO
SCALE 1
SUPPRESS-LEAD-ZEROES YES
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL YES
UNDEF-APT-CONT NO
M48
METRIC
T01C.5
T02C.8128
T03C.8999
T04C.9144
T05C1.
T06C1.1999
T07C3.302
;LEADER: 12
;HEADER:
;CODE : ASCII
;FILE : fmc_tlu_leds_pmt_pwr_21-1-4.drl for ... layers TOP and BOTTOM
;DESIGN: fmc_tlu_leds_pmt_pwr_21.brd
;T01 Holesize 1. = 0.500000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 89
;T02 Holesize 2. = 0.812800 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T03 Holesize 3. = 0.899900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 32
;T04 Holesize 4. = 0.914400 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
;T05 Holesize 5. = 1.000000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 16
;T06 Holesize 6. = 1.199900 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
;T07 Holesize 7. = 3.302000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 6
%
G90
T01
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